ASIC Verification Engineer

Snap Inc.

Hybrid Actively hiring Posted today Verified listing
Santa Monica, CA Posted today
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Salary context

How this pay compares to similar roles

Similar $185k
$130k most similar roles pay here $229k

This listing doesn't post a salary. Most similar roles pay $152,875–$216,250.

Based on 240 similar postings.

Employer

About Snap Inc.

Snap Inc. is a technology and camera company, best known for Snapchat, offering visual communication, augmented reality, and advertising products.

Snap Inc. currently has 55 open roles on FindRole.

Listed pay typically runs $209,000–$313,000 across 39 roles with salary data.

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At a glance

TL;DR

As an ASIC Verification Engineer at Snap Inc., you will join the Spectacles team, a world-class R&D group dedicated to developing cutting-edge wearable devices that integrate augmented reality. Your primary responsibility is to ensure the quality of AI ASIC designs by taking full ownership of complex IP blocks and subsystems, driving verification from specification through coverage sign-off using advanced UVM environments. You will collaborate cross-functionally to refine requirements and accelerate debugging efforts while shaping global verification methodologies. The role requires expertise in UVM, SystemVerilog, constraint-random verification, and deep knowledge of NPUs, image/video processing pipelines, and custom silicon architectures. Fluency in RTL languages like SystemVerilog and VHDL is essential, along with experience in modern CI/CD workflows and Git revision control. This position demands exceptional technical skills and the ability to thrive in a fast-paced, international environment dedicated to pushing the boundaries of AR technology.

Skills

UVM SystemVerilog constraint-random verification coverage-driven sign-off Artificial Intelligence tools NPUs image/video processing pipelines custom silicon architectures Synopsys front-end suites MIPI RTL VHDL CI/CD Git

What you'll do

  • Ensure the quality of AI ASIC designs for Spectacles wearable devices.
  • Own complex IP blocks and subsystems, leading verification efforts for edge AI and high-performance camera IPs.
  • Develop advanced UVM environments throughout project lifecycle from specifications to coverage sign-off.
  • Serve as a technical bridge, refining requirements and accelerating debugging through knowledge sharing across teams.
  • Shape global verification methodologies by launching initiatives to maintain best-in-class engineering standards.

What we're looking for

  • 5+ years of experience with UVM, SystemVerilog, and constraint-random verification.
  • Deep expertise in NPUs, image/video processing pipelines, or custom silicon architectures.
  • Proven ability to build sophisticated UVM test environments for custom IPs.
  • Fluency in RTL (SystemVerilog, Verilog, VHDL) and a passion for clean code.
  • Experience with modern CI/CD workflows and revision control systems like Git.
  • Strong technical leadership and cross-functional collaboration skills.
  • Clear communication skills for leading and collaborating in fast-paced projects.

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