ASIC Verification Engineer

Snap Inc.

Confirmed live yesterday High trust
Hybrid

Quick summary

Work type
Hybrid
Location
Eindhoven, Netherlands
Posted
100 days ago
Freshness
Confirmed live yesterday
Nearby
2 roles within 25 mi

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Salary context

How this pay compares to similar roles

Similar $188k
$132k most similar roles pay here $232k

This listing doesn't post a salary. Most similar roles pay $162,000–$214,000.

Based on 240 similar postings.

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About Snap Inc.

Snap Inc. is a technology and camera company, best known for Snapchat, offering visual communication, augmented reality, and advertising products.

Snap Inc. currently has 76 open roles on FindRole.

Listed pay typically runs $209,000–$313,000 across 58 roles with salary data.

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At a glance

TL;DR · ASIC Verification Engineer

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As an ASIC Verification Engineer on the Spectacles team, you will ensure the quality of AI ASIC designs for wearable devices. You will take full ownership of complex IP blocks and subsystems, specifically focusing on edge AI, high-performance camera, and next-generation display IPs. Your daily responsibilities include driving the project lifecycle from influencing specifications to developing advanced UVM environments and achieving coverage sign-off while collaborating cross-functionally to refine requirements and debug issues. The role requires expertise in UVM, SystemVerilog, constraint-random verification, and coverage-driven sign-off. You will utilize Synopsys front-end suites, Git for revision control, and CI/CD workflows. Technical skills include proficiency in RTL (SystemVerilog, Verilog, VHDL), knowledge of NPUs, image/video processing pipelines, and peripherals like MIPI. This role solves complex verification puzzles within the emerging augmented reality market to power advanced silicon nodes.

Skills

UVM SystemVerilog Verilog VHDL ASIC Verification Constraint-Random Verification Coverage-Driven Sign-off RTL Synopsys CI/CD Git MIPI AI

What you'll do

  • Verify AI ASIC designs for wearable devices to ensure high quality and performance.
  • Take ownership of complex IP blocks including edge AI, camera, and display systems.
  • Develop advanced UVM test environments from the ground up using SystemVerilog and Synopsys tools.
  • Manage the full project lifecycle from influencing specifications to achieving coverage sign-off.
  • Integrate Artificial Intelligence tools to automate and enhance verification workflows.
  • Act as a technical bridge to refine requirements and accelerate cross-functional debugging efforts.
  • Develop and implement new global verification methodologies for the engineering organization.

What we're looking for

  • You must have 5+ years of experience in UVM, SystemVerilog, constraint-random verification, and coverage-driven sign-off.
  • You must possess deep technical expertise in NPUs, image/video processing pipelines, or custom silicon architectures.
  • You must be able to build sophisticated UVM test environments from the ground up for custom IPs.
  • You should have knowledge of verifying peripherals related to image/video processing, such as MIPI.
  • You must be fluent in RTL languages including SystemVerilog, Verilog, and VHDL.
  • You must be able to navigate modern CI/CD workflows and version control using Git.
  • You must demonstrate a drive to use Artificial Intelligence tools to automate and enhance verification effectiveness.
  • You must possess strong interpersonal and communication skills to collaborate in a fast-paced environment.

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