Senior ASIC Verification Engineer, Coherent High Speed Interconnect

Nvidia

Hybrid

Quick summary

Work type: Hybrid
Location: Santa Clara, CAWestford, MAAustin, TXHillsboro, OR
Salary: $136,000–$218,500 / yr
Posted: 5 days ago
Nearby: 99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $197k

This role $177k

$125k most similar roles pay here $241k

This role pays less than 60% of similar roles. Most pay $177,250–$216,250 — the shaded band above. At the midpoint, this role pays about $177k versus about $197k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 994 open roles on FindRole.

Listed pay typically runs $168,000–$270,250 across 977 roles with salary data.

Most-posted roles

View all roles at Nvidia

At a glance

TL;DR · Senior ASIC Verification Engineer, Coherent High Speed Interconnect

Apply Now Log in to save

Join our Coherent High Speed Interconnect team as a Senior ASIC Verification Engineer at NVIDIA, where you will play a crucial role in verifying the design and implementation of high-speed coherent interconnects for mobile SoCs and GPUs. Your daily responsibilities include defining verification scope, developing testbenches, BFMs, checkers, monitors, and coverage plans to ensure the correctness of complex designs. You’ll collaborate closely with architects, designers, emulation, and silicon verification teams on multifaceted projects ranging from consumer graphics to autonomous vehicles and AI. Ideal candidates have a strong background in System Verilog, UVM methodology, C++, and experience with tools like VCS and Debussy. Knowledge of industry-standard protocols such as PCIE, CXL, and CHI is beneficial.

Skills

SystemVerilog UVM C++ Python PCIe CXL CHI VCS Debussy GDB

What you'll do

Develop verification infrastructure including testbenches, BFMs, checkers, and monitors.
Define and execute comprehensive test/coverage plans to verify design correctness.
Collaborate with architects and designers on micro-architecture using advanced methodologies.
Verify high-speed coherent interconnect designs for mobile SoCs and GPUs.
Utilize random stimulus, functional coverage, and assertion-based verification techniques.

What we're looking for

3+ years of ASIC verification experience
Expertise in System Verilog and UVM methodology
Experience with random stimulus, functional coverage, and assertion-based verification
Background in verifying coherent high-speed interconnects
Knowledge of industry-standard protocols like PCIE, CXL, CHI
Strong debugging skills and analytical abilities
Proficiency in C++ programming and scripting

Hybrid

Save

Senior ASIC Design Verification Engineer

Nvidia

Santa Clara, CA 26 days ago $136,000–$218,500

Verilog SystemVerilog UVM SVA VCS Perl Tcl Makefiles Python LLMs Agentic AI frameworks VCS-XA Gate Level Simulation Formal Equivalence

Hybrid

Save