Low Power ASIC Engineer

Nvidia

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Work type
On-site
Location
Santa Clara, CA
Employment
Full-time
Posted
147 days ago
Freshness
Confirmed live today
Nearby
99+ roles within 25 mi

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About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1623 open roles on FindRole.

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At a glance

TL;DR · Low Power ASIC Engineer

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JOB TITLE: Low Power ASIC Engineer - New College Grad 2026 The Low Power DV team is seeking a New College Grad 2026 to support the research and development of energy-efficient GPU and SOC architectures. In this role, you will collaborate with Low Power Architecture, Design, and Software teams to understand next generation features. Your primary responsibilities include architecting and developing testbenches, infrastructure, and testplans to verify various power management solutions for AI, Automotive, GeForce, and Mobile products. You will utilize Verilog, SystemVerilog, and UVM while employing Incisive Low-Power or Synopsys VCS NLP and Verdi for debugging. Required technical knowledge includes multi VT, Clock gating, Power gating, Block Activity Power, and Dynamic Voltage-Frequency Scaling. You will also work to improve power-aware DV methodologies and influence EDA vendors to enhance simulation and debug efficiencies.

Skills

Verilog SystemVerilog UVM Incisive Low-Power Synopsys VCS Verdi Python Perl C C++ UPF DVFS Clock Gating Power Gating Multi VT Makefile SOC Architecture

What you'll do

  • Architect and develop testbenches, infrastructure, and testplans to verify power management solutions.
  • Verify various power management solutions for NVIDIA products across AI, Automotive, and Mobile sectors.
  • Develop and improve power-aware DV methodologies to enhance simulation and debug efficiencies.
  • Collaborate with Architecture, Design, and Software teams to understand next-generation features.
  • Influence EDA vendors to improve simulation and debug performance.
  • Apply low power design techniques such as multi VT, clock gating, and DVFS during verification.
  • Utilize Verilog, SystemVerilog, and UVM to perform hardware verification.
  • Perform debugging using tools such as Incisive Low-Power, Synopsys VCS NLP, and Verdi.

What we're looking for

  • Completed a BS, MS, or PhD in Electrical Engineering, Computer Engineering, or equivalent experience.
  • Understand low power design techniques such as multi VT, Clock gating, Power gating, Block Activity Power, and DVFS.
  • Possess a good understanding of processor architecture and related power management design or DV techniques.
  • Experience with Incisive Low-Power or Synopsys VCS NLP.
  • Strong debug skills and experience with Verdi.
  • Fluent in Verilog and SystemVerilog with an understanding of UVM.
  • Prior knowledge of Low Power Architecture, Low Power CV, and deep learning (preferred).
  • Good understanding of power intent in UPF format, Python, PERL, C, or C++ (preferred).

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