Low Power ASIC Engineer

Nvidia

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
Santa Clara, CA
Salary
$100,000–$166,750 / yr
Posted
101 days ago
Freshness
Confirmed live yesterday
Nearby
99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $184k
This role $133k
$86k most similar roles pay here $233k

This role pays less than 88% of similar roles. Most pay $152,875–$215,300 — the shaded band above. At the midpoint, this role pays about $133k versus about $184k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 896 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 876 roles with salary data.

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At a glance

TL;DR · Low Power ASIC Engineer

Role Posting Log in to save

As a Low Power ASIC Engineer - New College Grad 2026, you will join the Low Power DV team to develop state of the art GPUs for AI, Automotive, GeForce, and Mobile products. You will collaborate with Architecture, Design, and Software teams to understand next generation features while architecting and developing testbenches, infrastructure, and testplans to verify various power management solutions. The role involves improving power-aware verification methodologies and influencing EDA vendors to enhance simulation and debug efficiencies. Required skills include proficiency in Verilog, SystemVerilog, UVM, and Verdi, along with experience in Incisive Low-Power or Synopsys VCS NLP. You must understand low power design techniques like multi VT, Clock gating, Power gating, Block Activity Power, and Dynamic Voltage-Frequency Scaling. Additional preferred skills include Python, PERL, C, C++, and knowledge of UPF format for power intent.

Skills

Verilog SystemVerilog UVM Synopsys VCS Incisive Verdi UPF Python Perl C C++ Makefile Low Power Design Power Management DVFS Clock Gating Power Gating

What you'll do

  • Architect and develop testbenches, infrastructure, and testplans to verify power management solutions.
  • Verify various power management features for GPU, Automotive, GeForce, and Mobile products.
  • Collaborate with Architecture, Design, and Software teams to understand next-generation product features.
  • Develop and improve power-aware design verification methodologies.
  • Influence EDA vendors to improve simulation and debug efficiencies.
  • Utilize Verilog, SystemVerilog, and UVM to perform low-power design verification.
  • Debug complex hardware issues using tools like Verdi and Synopsys VCS NLP.

What we're looking for

  • Must have a BS, MS, or PhD in Electrical Engineering, Computer Engineering, or equivalent experience.
  • Must be fluent in Verilog and SystemVerilog with an understanding of UVM.
  • Must have strong debug skills and experience with Verdi.
  • Must be experienced with Incisive Low-Power or Synopsys VCS NLP.
  • Must understand low power design techniques such as multi VT, Clock gating, Power gating, Block Activity Power, and DVFS.
  • Must have a good understanding of processor architecture and related power management design/DV techniques.
  • Preferred knowledge of Low Power Architecture, Low Power CV, and deep learning.
  • Preferred skills include Python or PERL scripting, C/C++ knowledge, and experience with UPF format.

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