Low Power ASIC Engineer - New College Grad 2026

Nvidia

Actively hiring Posted this week Verified listing
Santa Clara, CA Posted 2 days ago $100,000–$166,750 / year
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Salary context

Below market

How this pay compares to similar roles

Similar $185k
This role $133k
$86k most similar roles pay here $233k

This role pays less than 88% of similar roles. Most pay $152,875–$216,250 — the shaded band above. At the midpoint, this role pays about $133k versus about $185k for comparable roles.

Based on 240 similar postings.

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About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 855 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 843 roles with salary data.

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At a glance

TL;DR

Join NVIDIA’s Low Power Design/Verification (DV) team as an ASIC Engineer for new college graduates in 2026, where you will work closely with architecture, design, and software teams to develop cutting-edge testbenches, infrastructure, and test plans for verifying power management solutions across AI, automotive, GeForce, and mobile products. Your role involves enhancing power-aware DV methodologies and influencing EDA vendors to improve simulation efficiency. Ideal candidates have a BS, MS, or PhD in Electrical or Computer Engineering with expertise in low-power design techniques like multi-VT, clock gating, and dynamic voltage-frequency scaling (DVFS). Proficiency in Verilog, SystemVerilog, UVM, Incisive Low-Power, Synopsys VCS NLP, and Verdi is essential, along with scripting skills in Python or Perl. Experience with UPF format for power intent and background in low-power architectures will be advantageous as you contribute to the development of energy-efficient GPU and SOC architectures at scale.

Skills

Incisive Low-Power Synopsys VCS NLP Verdi Verilog SystemVerilog UVM Python Perl C C++ UPF Makefile

What you'll do

  • Develop testbench infrastructure to verify power management solutions for NVIDIA products.
  • Architect test plans to ensure comprehensive verification of low-power features in GPUs.
  • Collaborate with architecture and design teams to understand next-generation power requirements.
  • Enhance power-aware DV methodologies by bringing creative ideas and influencing EDA vendors.
  • Debug complex issues using tools like Verdi to improve simulation efficiency.

What we're looking for

  • Recent BS, MS, or PhD in Electrical/Computer Engineering or equivalent experience.
  • Proficient in low power design techniques including multi VT, clock gating, and DVFS.
  • Experience with Incisive Low-Power or Synopsys VCS NLP for verification.
  • Strong debug skills using Verdi and fluency in Verilog/SystemVerilog/UVM.
  • Understanding of processor architecture (GPU preferred) and related power management.
  • Scripting abilities in Python/Perl, with knowledge of C/C++ a plus.

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