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Matlab Simulink Simplis Spice verilogAMS Python Perl Tcl Skill Cadence_Virtuoso Allegro HSpice Spectre Primesim XA Ansys Sigrity +12 more Show less

Perl Python Tcl Make SPICE Liberty models CI/CD +2 more Show less

Spice Perl Tcl Make RTL Logic Synthesis Verification Place and Route Design-for-test(DFT) Analog Circuit Design Mixed-Signal Analog Design Digital Circuit Design Security Attacks Detection EM/IR Analysis Static Timing Analysis Noise Analysis Loop Stability Analysis Monte-Carlo Analysis +13 more Show less

Perl Python Tcl Make SPICE Liberty models Deep Learning GPU Parallel Computing CI/CD +5 more Show less

Spice Perl Tcl Make RTL Logic Synthesis Verification Place and Route Design-for-test(DFT) Analog Circuit Design Mixed-Signal Analog Block Design Digital Circuit Design Security Attacks Detection Circuits EM/IR Analysis Static Timing Analysis Noise Analysis Loop Stability Analysis Monte-Carlo Analysis +13 more Show less

Python C++ PyTorch LangChain LangGraph EDA VLSI ASIC AI/ML Deep Learning Agentic Systems Autonomous Optimization CI/CD +8 more Show less

Python Perl TCL Shell SKILL STA Timing_analysis Power_analysis Noise_analysis EMIR_analysis Machine_learning CAD EDA Industry_standard_circuit_simulator Debug_tools +10 more Show less

Perl Python Verilog VHDL SPICE Tcl Make RTL Simulation tools Waveform debugging tools ASIC design flow Custom SRAM design Transistor-level circuit design Power analysis Timing characterization Circuit verification Scripting languages Automation methods +13 more Show less

Python Perl CAD SPICE Verilog VHDL SRAM ML accelerators non-volatile memories DC/DC converters digital on-chip sensors high speed clocking TDCs ATE mixed signal verification scripting languages device physics leakage mechanisms noise sources +14 more Show less

SPICE Perl Tcl Make DRC LVS Python C++ VHDL Verilog Git Jenkins CI/CD Linux Windows Submicron Process Technology Standard Cell Libraries Custom ROM Designs Deep Learning Simulations GPU Accelerated Computing +15 more Show less

SPICE Perl Tcl Make DRC LVS EM/IR noise high sigma variation automation algorithms scripting simulation tools deep submicron process issues standard cell libraries custom ROMs flip flops level shifters math cells register files SRAM +15 more Show less

Spice Python Perl Tcl Make RTL Logic Synthesis Verification Auto Place and Route STA PnR DRC LVS Power Gating Multi-Vt Post-Silicon Characterization Custom Circuit Design Semi-Custom Circuit Design +13 more Show less