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Circuit Design RTL Layout Spice EM/IR Analysis Static Timing Analysis PnR Logic Synthesis Python Perl Tcl Make Power Gating DRC LVS Post-Silicon Characterization Hardware Security AI/ML +13 more Show less

SRAM Design Transistor-level Circuit Design Cadence Virtuoso FinFET Nanosheet Digital Circuit Design Layout Capture Logical Verification Silicon Testing Sense-amplifiers Self-timed Logic SRAM Compiler Development Codex Claude Code +9 more Show less

Mixed Signal Design CMOS Cadence Verilog Matlab PLL Transceivers CDR Data Converters High-Speed IO Timing Analysis Signal Integrity Power Integrity Silicon Characterization Lab Instrumentation Nanotime +11 more Show less

Post-Silicon Validation Silicon Bring-up Python C/C++ PVT Analysis Power Integrity PDN Analysis Transistor Physics Oscilloscopes Spectrum Analyzers Data Pipelines AI Agents +7 more Show less

Circuit Design Cadence Virtuoso Python Perl SPICE Static Timing Analysis EM and IR Analysis Formal Verification Layout Data Analysis Memory Design +6 more Show less

Circuit Design Mixed-Signal Analog Digital Circuit Design Spice Simulation EM/IR Analysis Static Timing Analysis RTL Logic Synthesis Place and Route Design-for-Test (DFT) Perl Tcl Make ADC Op-Amp Transistor-level Analysis +11 more Show less

Circuit Design Mixed-Signal Analog Digital Circuit Design Spice EM/IR Analysis Static Timing Analysis RTL Logic Synthesis Place and Route Design-for-test (DFT) Perl Tcl Make Monte-Carlo ADC Op-Amp Hardware Security +12 more Show less

ASIC Virtuoso Perl TCL DRC LVS PPA Low Power Design SOC PDK DRM Circuit QA Layout Power Management Cells Level Shifters Retention Designs +11 more Show less

Circuit Design Standard Cell Library PPA Layout Optimization PNR RTL2GDSII Static Timing Analysis STA Process Monitor IP PDK SOC GPU CPU Flip Flops Level Shifters +10 more Show less

SRAM Design RTL SoC Design Circuit Design Schematic Capture DFT IR/EM Machine Learning Silicon Debug Memory Hierarchy Scripting Nanometer Device Physics +7 more Show less

VLSI SPICE Perl Tcl Make DRC LVS RTL Logic Synthesis Place and Route ROM SRAM Flip Flops Level Shifters EM/IR Automation +11 more Show less

Power Delivery Networks Power Management Matlab Simulink Simplis Spice verilogAMS Mixed-signal HSpice Spectre Primesim Cadence Virtuoso Allegro Ansys Sigrity Python Perl Tcl Skill S-parameters +15 more Show less

Circuit Design Standard Cell ROM SPICE Perl Tcl Make DRC LVS EM/IR SRAM Flip Flops Level Shifters Deep Submicron Layout Simulation Scripting Automation +13 more Show less

Circuit Design Standard Cell Characterization SPICE Python Perl Tcl Make Liberty Models OCV Digital Implementation Signoff Flows Automation Deep Submicron Process +8 more Show less

SRAM Design SoC Design RTL Circuit Design Schematic Capture DFT IR/EM Machine Learning Silicon Debug Memory Hierarchy Scripting +6 more Show less

Circuit Design Standard Cell Characterization Python Perl Tcl SPICE Liberty Models Make OCV Digital Implementation Signoff Flows Automation Deep Submicron Process +8 more Show less