Senior SRAM Circuit Design Engineer

Apple Inc

Quick summary

Work type: On-site
Location: Santa Clara, CA
Salary: $147,400–$272,100 / yr
Posted: 2 days ago
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $186k

This role $210k

$126k most similar roles pay here $288k

This role pays more than 71% of similar roles. Most pay $158,750–$214,093 — the shaded band above. At the midpoint, this role pays about $210k versus about $186k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1848 open roles on FindRole.

Listed pay typically runs $163,300–$272,100 across 1511 roles with salary data.

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At a glance

TL;DR · Senior SRAM Circuit Design Engineer

Role Posting Log in to save

Join Apple's Digital Custom Group as an SRAM Circuit Design Engineer, where you will collaborate with top-tier engineers to design high-performance custom digital circuits for SRAM in cutting-edge products like the M1 chip. Your daily tasks include formulating design specifications, optimizing power and timing, conducting simulations, and working closely with layout teams to ensure optimal GDS creation. You’ll also write RTL code, validate use cases, and support post-silicon efforts. Ideal candidates have experience in SoC design cycles, low-power SRAM/Register File development, cache architecture, and RTL modeling. Familiarity with machine learning algorithms and scripting is beneficial as you tackle complex challenges at the heart of Apple’s silicon innovation.

Skills

RTL Verilog VHDL Cadence Synopsys Tanner EDA Calibre Python Machine_Learning Git CI/CD Unix/Linux Cache_design Memory_hierarchy DFT GDSII

What you'll do

Design and implement custom digital circuits for SRAM in high-performance products.
Define architecture optimizing power, timing, area, and yield for SRAM designs.
Capture schematics, perform simulations, and verify margins for SRAM implementations.
Collaborate with layout team to create optimal GDS for SRAM designs.
Verify extracted GDS meets design specifications for SRAM circuits.
Write RTL code and validate use-cases against design schematics.

What we're looking for

Extensive experience in SRAM/Register File development for low power, low voltage, high performance SoCs.
Proven track record of working within the full SoC design cycle.
Deep understanding of cache design/architecture and memory hierarchy optimization.
Strong knowledge of RTL modeling and scripting for circuit implementation.
Ability to devise experiments and analyze data for effective silicon debug.
Familiarity with machine learning algorithms is highly beneficial.

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