SRAM Circuit Design Engineer

Apple Inc

Confirmed live today Low trust

Quick summary

Work type
On-site
Location
Santa Clara, CA
Salary
$184,700–$324,800 / yr
Posted
87 days ago
Freshness
Confirmed live today

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $198k
This role $255k
$129k $346k
below market most similar roles pay here above market

This role pays more than 96% of similar roles. Most pay $167,100–$229,100 — the blue band above. At the midpoint, this role pays about $255k versus about $198k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3497 open roles on FindRole.

Listed pay typically runs $174,149–$277,600 across 2702 roles with salary data.

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At a glance

TL;DR · SRAM Circuit Design Engineer

The SRAM Circuit Design Engineer joins the Digital Custom Group to design and implement custom digital circuits for SRAM. Working with the logic and architecture teams, the engineer defines topologies optimized for power, timing, area, and yield. Daily responsibilities include schematic capture, simulations, margin verifications, functional equivalency, and DFT modeling. The role involves writing RTL, validating use-cases, and collaborating with layout teams to create optimal GDS while performing backend verification for IR and EM. Candidates must possess expertise in nanometer device physics, leakage mechanisms, and SoC design cycles for low power and high performance. The position specifically addresses memory hierarchy and cache design challenges to support CPU, GPU, SoC, Neural Engine, and Camera designs within custom silicon products.

What you'll do

  • Design and implement custom digital circuits for SRAM design.
  • Define architecture and topologies to optimize for power, timing, area, and yield.
  • Perform schematic capture, simulations, analysis, and margin verifications.
  • Execute functional equivalency and DFT modeling.
  • Collaborate with the layout team to create and verify optimal GDS.
  • Perform backend verification, including IR and EM analysis.
  • Write RTL and validate use-cases against design schematics.
  • Support post-silicon efforts to enable productization.

What we're looking for

  • Minimum of 10 years relevant industry experience.
  • Experience developing circuits and SRAM/Register Files for low power, low voltage, and high performance (preferred).
  • Knowledge of Cache design/architecture and memory hierarchy (preferred).
  • Working knowledge of RTL modeling (preferred).
  • Solid understanding of industry-standard design tools (preferred).
  • Deep understanding of nanometer device physics, leakage mechanisms, and technology interactions with device behavior (preferred).
  • Ability to devise experiments and analyze data for silicon debug (preferred).

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