Circuit Design Engineer, Library/Process Monitor

Apple Inc

Confirmed live yesterday Trusted

Quick summary

Work type: On-site
Location: Santa Clara, CA
Salary: $150,400–$277,600 / yr
Posted: 83 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

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Competitive pay

How this pay compares to similar roles

Similar $203k

This role $214k

$135k $293k

below market most similar roles pay here above market

This role pays more than 62% of similar roles. Most pay $165,975–$240,550 — the blue band above. At the midpoint, this role pays about $214k versus about $203k for comparable roles.

Based on 240 similar postings.

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3497 open roles on FindRole.

Listed pay typically runs $174,149–$277,600 across 2702 roles with salary data.

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At a glance

TL;DR · Circuit Design Engineer, Library/Process Monitor

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Circuit Design Engineer - Library/Process Monitor joins the Digital Design Engineering group to support processor design efforts using deep submicron technologies. This role involves working with the custom digital circuits team and library development to design standard cell circuits and process monitor IP. Key responsibilities include driving transistor level circuit design, modeling, and performance analysis while optimizing library architecture to improve overall PPA. The engineer will identify and reduce parasitics, manage PPA for various technology and PDK releases, and engage with CPU, SOC, and GPU teams on physical design requirements. Required skills include circuit design for high-performance flip flops, level shifters, and retention flops. Candidates should also possess experience with RTL2GDSII flow and Static Timing Analysis to ensure functional products reach customers quickly.

Skills

Circuit Design Standard Cell Library PPA Layout Optimization PNR RTL2GDSII Static Timing Analysis STA Process Monitor IP PDK SOC GPU CPU Flip Flops Level Shifters

What you'll do

Drive transistor-level circuit design, modeling, and performance analysis for deep submicron technologies.
Develop standard cell circuits to improve overall Power, Performance, and Area (PPA).
Optimize library architecture to enhance PPA across different technologies, architectures, and PDK releases.
Identify and reduce parasitics to drive layout optimization efforts.
Design process monitor IP on PNR blocks and validate other IPs in testchips.
Communicate and define physical design requirements for CPU, SOC, and GPU teams.

What we're looking for

Minimum of 3 years of experience.
Experience in circuit design of high-performance flip flops, level shifters, retention flops, and other complex circuits (preferred).
Experience in RTL2GDSII flow and/or Static Timing Analysis (STA) (preferred).
Bachelor's Degree.

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