Circuit Design Engineer, Library

Apple Inc

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Quick summary

Work type: On-site
Location: Santa Clara, CA
Salary: $150,400–$277,600 / yr
Posted: 67 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

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Competitive pay

How this pay compares to similar roles

Similar $200k

This role $214k

$130k $293k

below market most similar roles pay here above market

This role pays more than 62% of similar roles. Most pay $167,375–$231,737 — the blue band above. At the midpoint, this role pays about $214k versus about $200k for comparable roles.

Based on 240 similar postings.

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About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3497 open roles on FindRole.

Listed pay typically runs $174,149–$277,600 across 2702 roles with salary data.

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TL;DR · Circuit Design Engineer, Library

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JOB TITLE: Circuit Design Engineer - Library As a Circuit Design Engineering Lead within the Digital Design Engineering group, you will lead a custom circuits team and library development for state-of-the-art ASIC and processor designs. You will drive the development of high-performance, low-power optimized standard cells, level shifters, and retention designs to improve PPA. Your daily responsibilities include identifying next-generation ideas, performing circuit QA checks, and managing migrations to new PDKs. You will collaborate with CPU, SOC, and GPU teams on chip-level integration while working with foundries on DRM compliant layout checkers. Required skills include experience with standard cell circuit development, Virtuoso, DRM, DRC/LVS decks, and PDV flows. You must also possess knowledge of circuit robustness analysis and experience scripting in Perl and/or TCL to solve complex silicon design problems.

Skills

ASIC Virtuoso Perl TCL DRC LVS PPA Low Power Design SOC PDK DRM Circuit QA Layout Power Management Cells Level Shifters Retention Designs

What you'll do

Drive development of high-performance, low-power optimized standard cells to improve design PPA.
Develop optimal level shifters and retention designs to meet low-power requirements.
Identify and implement next-generation ideas to further improve PPA.
Coordinate with CPU, SOC, and GPU teams on chip-level integration requirements.
Perform circuit QA checks and develop new methodologies based on design requirements.
Collaborate with foundries on DRM compliant layout checkers and iPDK requirements.
Manage migrations to new PDKs and oversee PDV of standard cells and releases.

What we're looking for

Minimum of 3 years of experience.
3+ years of experience in Standard cells circuit development (preferred).
Proven experience in developing, driving, and implementing circuit methodologies (preferred).
Proven experience leading and mentoring a small team (preferred).
Knowledge of standard cell layout, DRM, DRC/LVS decks, PDV flows, and Virtuoso (preferred).
Design experience in advanced tech node device behavior with understanding of layout rules (preferred).
Experience in scripting in Perl and/or TCL (preferred).
Bachelor's Degree.

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