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Active Keyword: Senior ASIC Engineer Remove filter Location: San Jose Remove filter Clear all

6 of up to 20 (filtered)

Senior ASIC Engineer

Cisco

San Jose, CA 8 days ago $167,700–$245,200
Actively hiring Confirmed live 2 days ago High trust Above market
ASIC System Verilog UVM Veloce Palladium Zebu HAPS C C++ Python Perl Linux Networking Post-silicon Lab Bring-up Verification Methodology Silicon One
7+ yrs exp Hybrid
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Senior Chip Lead Engineer SoC/ASIC

Amd

San Jose, CA 8 days ago $164,000–$246,000
Actively hiring Confirmed live yesterday High trust Competitive pay
ASIC FPGA RTL Verilog SystemVerilog VHDL EDA Tools Physical Design Timing Closure Power Optimization DFT Silicon Validation Device Drivers Low-level Software AI/ML Accelerators
10+ yrs exp
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Senior ASIC Design Engineer

Cisco

Remote (San Jose, CA) 30 days ago $167,700–$245,200
Actively hiring Confirmed live yesterday Trusted Competitive pay
Verilog System Verilog ASIC Design RTL Timing Closure Clock Gating post silicon validation Scripting Micro-architecture
7+ yrs exp Remote
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Senior Custom ASIC Engineering Lead

Broadcom

San Jose, CA 44 days ago $143,800–$230,000
Actively hiring Confirmed live 2 days ago High trust Competitive pay
Physical Design STA DFT EDA Tools TCL Verilog RTL Logic Synthesis Low Power Design SERDES DRC Scan Memory BIST Chip Architecture Packaging Tape-out
10+ yrs exp
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Senior Custom ASIC Engineering Lead

Broadcom

San Jose, CA +2 85 days ago $143,800–$230,000
Actively hiring Confirmed live yesterday High trust Competitive pay
Physical Design STA DFT EDA Tools TCL Verilog RTL Logic Synthesis SERDES Low Power Design Packaging Tape-out DRC Scan Memory BIST Microarchitecture
10+ yrs exp
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Senior Custom ASIC Engineering Lead

Broadcom

San Jose, CA +2 85 days ago $143,800–$230,000
Actively hiring Confirmed live 2 days ago High trust Competitive pay
Physical Design STA DFT TCL Verilog RTL Logic Synthesis SERDES Low Power Design EDA Tools Tape-out Packaging Logic Simulation DRC Memory BIST
10+ yrs exp
Save