Browse tech roles

Basic role filtering by workplace, salary floor, and post age. For full AI matching and advanced filtering upload your resume using AI Match.

Active Keyword: Senior ASIC Engineer Remove filter Location: San Jose Remove filter Clear all

12 of up to 20 (filtered)

Senior ASIC Design Verification Engineer

Cisco

San Jose, CA 6 days ago $167,700–$245,200
Actively hiring Confirmed live today Posted this week High trust Competitive pay
ASIC Design Verification System Verilog UVM Python Perl Gate Level Simulation Emulation Formal Verification PCIe CXL Ethernet RDMA DDR TCP P4 Veloce Palladium Zebu HAPS OOP
7+ yrs exp
Save

Senior ASIC RTL Engineer

Cisco

San Jose, CA +1 6 days ago $167,700–$245,200
Actively hiring Confirmed live today Posted this week High trust Competitive pay
Verilog System Verilog DFT MBIST AMBA AXI APB AHB JTAG UPF Formal Verification Linting CDC Checkers Synthesis Post-Silicon Debug Power Optimization Power Estimation
7+ yrs exp Hybrid
Save

Senior ASIC DFT DV Engineer

Cisco

San Jose, CA +1 13 days ago $167,700–$245,200
Actively hiring Confirmed live today High trust Competitive pay
System Verilog UVM Python TCL Perl Verdi DVE JTAG MBIST DFT Scan Architecture Boundary Scan ATE post silicon validation
7+ yrs exp Hybrid
Save

Senior ASIC DFT DV Engineer

Cisco

San Jose, CA 14 days ago $167,700–$245,200
Actively hiring Confirmed live today High trust Competitive pay
DFT MBIST ATE Verilog Python TCL Perl DVE Verdi SRAM DRAM Synopsys DesignWare SMS TestMax Mentor Graphics Tessent
7+ yrs exp Hybrid
Save

Senior ASIC Engineer, Post Silicon Validation

Cisco

San Jose, CA 27 days ago
Actively hiring Confirmed live yesterday High trust
ASIC Post-Silicon Validation Python C System Verilog UVM PCIe Ethernet I2C SPI JTAG Firmware Bootloaders DFT ATE Oscilloscopes Traffic Generators HBM DDR
7+ yrs exp
Save

Senior ASIC Engineer, Post Silicon Validation

Cisco

San Jose, CA 47 days ago
Actively hiring Confirmed live yesterday Trusted
ASIC Post-Silicon Validation Python C System Verilog UVM PCIe Ethernet I2C SPI JTAG DFT Firmware Bootloaders HBM DDR Oscilloscopes Traffic Generators Regression Frameworks
7+ yrs exp
Save

Senior ASIC Engineer

Cisco

San Jose, CA 53 days ago $167,700–$245,200
Actively hiring Confirmed live yesterday High trust Above market
ASIC Design System Verilog UVM Post-silicon Lab Bring-up C/C++ Python Perl Linux Veloce Palladium Zebu HAPS Networking
7+ yrs exp
Save

Senior Chip Lead Engineer, SoC/ASIC

Amd

San Jose, CA 54 days ago $164,000–$246,000
Actively hiring Confirmed live yesterday High trust Competitive pay
ASIC FPGA Verilog SystemVerilog VHDL RTL Design DFT Physical Design Timing Closure Power Optimization EDA Tools Silicon Validation Device Drivers System Software AI/ML Accelerators CPU GPU
10+ yrs exp
Save

Senior ASIC Design Engineer

Cisco

San Jose, CA 75 days ago
Actively hiring Confirmed live yesterday Trusted
Verilog System Verilog ASIC Design RTL Timing Closure Clock Gating Post Silicon Validation Scripting Micro-architecture Place-and-Route Functional Coverage
7+ yrs exp
Save

Senior Custom ASIC Engineering Lead

Broadcom

San Jose, CA 89 days ago $143,800–$230,000
Actively hiring Confirmed live today Trusted Competitive pay
Physical Design STA DFT TCL Verilog Logic Synthesis DRC SERDES Logic Simulation Power Management Memory BIST Scan Packaging Tape-out EDA Tools
10+ yrs exp
Save

Senior Custom ASIC Engineering Lead

Broadcom

San Jose, CA +2 130 days ago $143,800–$230,000
Actively hiring Confirmed live today Trusted Competitive pay
Physical Design STA DFT TCL Verilog EDA Tools Logic Synthesis DRC SERDES Logic Simulation Power Management Scan Memory BIST Chip Architecture
10+ yrs exp
Save

Senior Custom ASIC Engineering Lead

Broadcom

San Jose, CA +2 130 days ago $143,800–$230,000
Actively hiring Confirmed live today Trusted Competitive pay
Physical Design STA DFT Packaging EDA Tools TCL Verilog RTL Logic Synthesis DRC SERDES Scan Memory BIST Logic Simulation Low Power Design
10+ yrs exp
Save