Senior ASIC Engineer

Cisco

Confirmed live yesterday High trust
Hybrid

Quick summary

Work type
Hybrid
Location
San Jose, CA
Salary
$167,700–$245,200 / yr
Posted
7 days ago
Freshness
Confirmed live yesterday
Closes
Nov 30, 2026

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $191k
This role $206k
$132k most similar roles pay here $257k

This role pays more than 67% of similar roles. Most pay $166,538–$216,250 — the shaded band above. At the midpoint, this role pays about $206k versus about $191k for comparable roles.

Based on 240 similar postings.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 196 open roles on FindRole.

Listed pay typically runs $167,700–$245,200 across 196 roles with salary data.

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At a glance

TL;DR · Senior ASIC Engineer

As a Senior ASIC Engineer within the Common Hardware Group, you will contribute to the development of high-performance hardware platforms for switching, routing, and wireless products. You will drive the definition, architecture, design, and verification of ASICs while owning complex functional areas and developing reusable code for future projects. Your daily responsibilities include debugging at the ASIC, software, and hardware levels, leading design and verification work to resolve block-level issues, and implementing power-saving solutions. The role requires expertise in SystemVerilog, UVM, and tools like Veloce, Palladium, Zebu, or HAPS. You will also utilize Linux, C/C++, and Python or Perl to support the development cycle. This position focuses on solving complex hardware challenges within the networking domain to power core infrastructure for the AI era.

What you'll do

  • Drive the definition, architecture, design, and verification of high-performance ASICs.
  • Own complex functional areas and develop reusable code for future projects.
  • Debug issues across ASIC, software, and hardware levels.
  • Resolve block-level issues and participate in chip-level problem resolution.
  • Define new verification methodologies and lead platform-level code reviews.
  • Identify and implement power-saving solutions for hardware components.
  • Assist with post-silicon lab bring-up processes.

What we're looking for

  • Bachelor's degree plus 7 years of related experience, or Master's plus 4 years, or PhD plus 2 years.
  • Experience with ASIC design and verification processes using System Verilog.
  • Proficiency in debugging at the ASIC, software, and hardware levels.
  • Experience with UVM for leading verification methodology of clusters, subsystems, or full chips.
  • Experience with emulation platforms such as Veloce, Palladium, Zebu, or HAPS.
  • Proficiency in Linux, C/C++, and/or Python/Perl.
  • Experience in the networking field.
  • Experience with post-silicon lab bring-up.

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