Senior ASIC Engineer

Cisco

Confirmed live today High trust

Quick summary

Work type
On-site
Location
San Jose, CA
Salary
$167,700–$245,200 / yr
Employment
Full-time
Posted
53 days ago
Freshness
Confirmed live today
Closes
Nov 30, 2026
Nearby
99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $189k
This role $206k
$134k $257k
below market most similar roles pay here above market

This role pays more than 66% of similar roles. Most pay $162,000–$216,250 — the blue band above. At the midpoint, this role pays about $206k versus about $189k for comparable roles.

Based on 240 similar postings.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 307 open roles on FindRole.

Listed pay typically runs $167,700–$245,000 across 224 roles with salary data.

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At a glance

TL;DR · Senior ASIC Engineer

Role Posting Log in to save

The Senior ASIC Engineer joins the Common Hardware Group to develop innovative hardware platforms for switching, routing, and wireless products. This role involves driving the definition, architecture, design, and verification of high-performance ASICs while owning complex functional areas. Day-to-day responsibilities include developing reusable code, debugging at the ASIC, software, and hardware levels, and leading design and verification work to resolve block-level issues. The engineer will also identify power-saving solutions, define new verification methodologies, and assist in lab bring-up. Required technical skills include experience with ASIC design and verification processes using SystemVerilog, as well as debugging tools. Preferred qualifications include UVM methodology, experience with emulation platforms like Veloce, Palladium, Zebu, or HAPS, and proficiency in Linux, C/C++, Python, or Perl within a networking context.

Skills

ASIC Design System Verilog UVM Post-silicon Lab Bring-up C/C++ Python Perl Linux Veloce Palladium Zebu HAPS Networking

What you'll do

  • Drive the definition, architecture, design, and verification of high-performance ASICs.
  • Own complex functional areas and lead design and verification work to solve block-level issues.
  • Develop and maintain reusable code for future projects.
  • Debug issues at the ASIC, software, and hardware levels.
  • Define new verification methodologies and lead code reviews at the platform level.
  • Identify, design, and implement power-saving solutions.
  • Assist in lab bring-up and participate in chip-level issue resolution.

What we're looking for

  • Bachelors + 7 years of related experience, or Masters + 4 years of related experience, or PhD + 2 years of related experience.
  • Experience with ASIC design and verification processes using System Verilog, debugging, methodology, and tools.
  • Experience with dashboard management for regression, coverage, test list completion, and other DV statistics (preferred).
  • Post-silicon lab bring-up experience (preferred).
  • Experience leading verification methodology in UVM for clusters, subsystems, or full chip level for ASIC (preferred).
  • Experience using emulation platforms such as Veloce, Palladium, Zebu, or HAPS (preferred).
  • Experience with Linux, C/C++, and/or Python/Perl (preferred).
  • Experience in Networking (preferred).

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