Senior ASIC Engineer, Post Silicon Validation

Cisco

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
San Jose, CA
Employment
Full-time
Posted
31 days ago
Freshness
Confirmed live yesterday
Closes
Nov 10, 2026
Nearby
99+ roles within 25 mi

Market check

Salary context

How this pay compares to similar roles

Similar $192k
$140k $245k
below market most similar roles pay here above market

This listing doesn't post a salary. Most similar roles pay $168,425–$216,562.

Based on 240 similar postings.

Employer

About Cisco

Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity

Cisco currently has 261 open roles on FindRole.

Listed pay typically runs $167,700–$245,000 across 197 roles with salary data.

Most-posted roles

View all roles at Cisco

At a glance

TL;DR · Senior ASIC Engineer, Post Silicon Validation

Role Posting Log in to save

The Senior ASIC Engineer - Post Silicon Validation joins the Silicon One team to develop hardware platforms for switching, routing, and wireless products. This role involves planning and setting up silicon bring-up infrastructure, including system boot and power-on of ASICs. You will root-cause functional and electrical issues while executing validation test plans for IP, subsystem, and full-chip stress testing. Key responsibilities include developing automation frameworks, using lab instrumentation like oscilloscopes and traffic generators, and providing feedback on silicon errata. The position requires proficiency in C, Python, and scripting, alongside experience with PCIe, Ethernet, I2C, SPI, and JTAG protocols. You will also utilize System Verilog, UVM, and emulation-based verification to ensure a smooth transition from pre-silicon verification to post-silicon validation for complex hardware systems.

Skills

ASIC Post-Silicon Validation Python C System Verilog UVM PCIe Ethernet I2C SPI JTAG DFT Firmware Bootloaders HBM DDR Oscilloscopes Traffic Generators Regression Frameworks

What you'll do

  • Plan and set up silicon bring-up infrastructure including system boot, initialization, and ASIC power-on.
  • Root-cause and resolve functional and electrical issues in coordination with design, verification, and board teams.
  • Prepare and execute validation test plans for IP, subsystem, and full-chip stress testing.
  • Develop and extend post-silicon validation infrastructure, automation, and test suites for result capture and regression.
  • Use lab instrumentation like oscilloscopes, analyzers, and traffic generators for validation and characterization.
  • Provide feedback on test escapes, yield issues, and silicon errata to influence revisions and firmware workarounds.

What we're looking for

  • Bachelor's degree in Electrical or Computer Engineering with 7+ years experience, a Master's with 4+ years, or a PhD with 1+ years.
  • Prior experience in post-silicon validation, bring-up, and debug with ASICs.
  • Prior experience in early silicon bring-up, debug, and validation.
  • Prior experience bringing up standard peripheral interfaces (I2C, SPI, JTAG) and protocols (PCIe, Ethernet).
  • Prior experience with firmware, bootloaders, and low-level silicon debug environments.
  • Fluency in C, Python, and scripting for validation automation.
  • Experience with memory subsystems (HBM, DDR) (preferred).
  • Experience with electrical and thermal performance characterization activities (preferred).
  • Experience with System Verilog/UVM-based verification and emulation-based verification (preferred).

Related searches

More Senior ASIC Engineer jobs Senior ASIC Engineer jobs in San Jose All jobs at Cisco

More like this

Similar roles

Senior ASIC Engineer, Post Silicon Validation

Cisco

San Jose, CA 11 days ago $167,700–$245,200
ASIC Post-Silicon Validation Python C System Verilog UVM PCIe Ethernet I2C SPI JTAG DFT RTL Firmware HBM DDR Oscilloscope Traffic Generators Regression Frameworks
7+ yrs exp
Save

Senior ASIC Verification Engineer

Nvidia

Westford, MA +1 54 days ago $136,000–$218,500
SystemVerilog UVM ASIC Design Ethernet NVLink USB SATA CXL Python Perl Assertion-Based Verification Functional Coverage coverage driven verification High Speed I/O
5+ yrs exp
Save

ASIC Design Verification Engineering Leader

Cisco

San Jose, CA 68 days ago
SystemVerilog UVM Verilog Python Perl C/C++ Linux ASIC Design Formal Verification PCIe Ethernet RDMA TCP Fiber Channel P4 Veloce Palladium Zebu HAPS Jasper Gold
10+ yrs exp
Save

Senior ASIC Verification Engineer

Nvidia

Santa Clara, CA 87 days ago
SystemVerilog UVM C++ VCS Assertion-Based Verification Random Stimulus Functional Coverage GDB Debussy Computer Architecture Object-Oriented Programming Processor Pipeline Verification
6+ yrs exp Hybrid
Save

Senior ASIC Verification Engineer

Nvidia

Austin, TX 5 days ago $136,000–$218,500
System Verilog UVM Python Verilog RTL VCS Verdi OOPS ASIC Verification Computer Architecture Functional Coverage Scripting
3+ yrs exp
Save

Senior ASIC Verification Engineer

Nvidia

Santa Clara, CA +4 6 days ago $136,000–$218,500
System Verilog UVM C++ Python Perl ASIC Verification Formal Verification Constraint Random Verification Logic Design Coverage Metrics DFT IST Object-Oriented Programming X prop
5+ yrs exp Hybrid
Save