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Active Keyword: RTL Remove filter Location: San Jose Remove filter Clear all

12 of up to 20 (filtered)

RTL Tools & Methodology Engineer

Amd

San Jose, CA 3 days ago $141,760–$212,640
Actively hiring Confirmed live today Posted this week High trust Competitive pay
RTL SystemVerilog Verilog VHDL Lint CDC Formal Equivalence Low-power Verification Python Perl TCL FPGA Static Verification Logic Design
Hybrid
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Senior RTL Design Engineer

Amd

San Jose, CA 9 days ago $200,000–$300,000
Actively hiring Confirmed live today High trust Above market
Verilog SystemVerilog UVM Python Tcl Perl Shell DFT STA ASIC SoC FPGA Synopsys Cadence VCS PrimeTime GDS HBM PCIe SerDes
Hybrid
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RTL Design Manager

Amd

San Jose, CA 10 days ago $186,400–$279,600
Actively hiring Confirmed live today High trust Above market
RTL SoC Arm Architecture APB AXI CHI Python Perl Tcl UPF LINT CDC Timing Constraints Front-end Design Verification
Hybrid
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Senior Engineer, GPU RTL Design

Samsung Electronics

San Jose, CA 13 days ago $139,000–$208,400
Actively hiring Confirmed live today High trust Below market
Verilog SystemVerilog RTL Design GPU Architecture ASIC Design Synthesis Timing Analysis Linting Microarchitecture Digital Design SoC
2+ yrs exp
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RTL / Circuit IP Design Engineer

Amd

San Jose, CA 19 days ago $166,400–$249,600
Actively hiring Confirmed live today High trust Competitive pay
RTL System Verilog Verilog UVM Python Perl Ruby Makefile Linux Windows HLS UPF Synthesis Timing Analysis Circuit Design Simulation Tools
Hybrid
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SerDes RTL Design Engineer

Amd

San Jose, CA 22 days ago $166,400–$249,600
Actively hiring Confirmed live today High trust Competitive pay
RTL Verilog System Verilog SerDes PMA PCS Python Perl TCL CMOS Static Timing Analysis LINT CDC RDC Digital Signal Processing Low Power Design Mixed Signal Design PPA Analysis
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RTL Design & Integration Engineer

Amd

San Jose, CA 43 days ago $166,400–$249,600
Actively hiring Confirmed live today High trust Competitive pay
Verilog SystemVerilog RTL Design VLSI FPGA Python Tcl Perl Shell Synopsys Design Compiler Primetime VCS Cadence Virtuoso UVM OVM STA Synthesis P&R GDSII
Hybrid
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Senior RTL Engineer, IO Die and Interconnect IP

Samsung Semiconductor

San Jose, CA 44 days ago $138,000–$206,000
Actively hiring Confirmed live today High trust Below market
Verilog SystemVerilog RTL Design UCIe PCIe CXL NoC SoC Integration IP-XACT AXI ACE CHI APB Python Tcl Perl AI/ML Agentic AI
5+ yrs exp
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Senior RTL Engineer, Memory Centric Computing

Samsung Semiconductor

San Jose, CA 46 days ago $138,000–$206,000
Actively hiring Confirmed live today High trust Below market
Verilog System Verilog HLS RTL Microarchitecture Computer Architecture Memory Controller NoC Interconnect IP SoC Integration AI/ML Pipelining Data Compression
5+ yrs exp
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RTL Integration Engineer

Broadcom

San Jose, CA 65 days ago $143,800–$230,000
Actively hiring Confirmed live today High trust Competitive pay
SystemVerilog UVM RTL Design Synthesis STA CDC RDC Gate-level Simulation SDF NCSim VCS Palladium Modeling Linting
10+ yrs exp
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Digital Design RTL Engineer

Broadcom

Fort Collins, CO +1 72 days ago
Actively hiring Confirmed live today High trust
SystemVerilog RTL Design PPA Optimization CDC) analysis RDC Low-Power Design SoC Integration SerDes LPDDR DDR HBM Timing Closure Physical Design Advanced Process Nodes
5+ yrs exp
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Digital Design RTL Engineer

Broadcom

Fort Collins, CO +1 74 days ago $121,900–$195,000
Actively hiring Confirmed live today High trust Below market
SystemVerilog RTL Design PPA Optimization Clock Domain Crossing (CDC) Reset Domain Crossing (RDC) Low-Power Design SoC Integration LPDDR5 DDR4 DDR5 SerDes HBM Timing Closure Physical Design
8+ yrs exp
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