RTL Design Manager

Amd

Confirmed live today High trust
Hybrid

Quick summary

Work type
Hybrid
Location
San Jose, CA
Salary
$186,400–$279,600 / yr
Posted
9 days ago
Freshness
Confirmed live today
Closes
Sep 24, 2027

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $208k
This role $233k
$151k most similar roles pay here $293k

This role pays more than 70% of similar roles. Most pay $171,717–$243,600 — the shaded band above. At the midpoint, this role pays about $233k versus about $208k for comparable roles.

Based on 240 similar postings.

Employer

About Amd

AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors

Amd currently has 512 open roles on FindRole.

Listed pay typically runs $166,400–$249,600 across 512 roles with salary data.

Most-posted roles

View all roles at Amd

At a glance

TL;DR · RTL Design Manager

As an RTL Design Manager within the AECG IP & SOC group, you will join the front-end design and integration team to deliver cutting-edge designs. You will lead a high-performance engineering team to own the design and implementation of blocks that meet specific functional, timing, area, and power requirements while guiding verification processes. Your daily work involves designing logic functions for efficient test and debug, implementing automation to increase team efficiency, and collaborating with architecture, IP design, physical design, and product engineers to achieve first pass silicon success. The role requires expertise in front-end RTL engineering, Arm architecture, and APB, AXI, and CHI protocols. You will utilize scripting languages like PERL, Python, or Tcl for automation while managing timing constraints, LINT and CDC checks, and UPF for multiple power domains.

What you'll do

  • Lead a small, high-performance engineering team of senior silicon design engineers.
  • Own the design and implementation of blocks to meet functional, timing, area, and power requirements.
  • Guide and review verification processes for specific hardware blocks.
  • Design and implement logic functions to enable efficient test and debug.
  • Develop automation scripts using Python, Perl, or Tcl to increase team efficiency.
  • Manage SoC level design integration across various architecture and IP teams.
  • Resolve complex technical problems by analyzing behavior and designing experiments for improvement.

What we're looking for

  • Bachelor's or Master's degree in computer engineering or Electrical Engineering.
  • Strong front-end RTL engineering background.
  • Ability to lead a small, high-performance engineering team.
  • Strong communication skills to summarize complex problems for executives and technical details for engineers.
  • Strong analytical and problem-solving skills including the ability to analyze behavior and design experiments.
  • Experience with Arm architecture and APB, AXI, CHI protocols (preferred).
  • Experience with design reuse, SoC level integration, and timing constraints/exceptions (preferred).
  • Experience with scripting (Perl, Python, Tcl), LINT/CDC checks, and UPF for multiple power domains (preferred).

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