RTL Integration Engineer

Broadcom

Confirmed live today High trust

Quick summary

Work type
On-site
Location
San Jose, CA
Salary
$143,800–$230,000 / yr
Employment
Full-time
Posted
65 days ago
Freshness
Confirmed live today
Closes
Jan 27, 2027
Nearby
99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $193k
This role $187k
$133k most similar roles pay here $240k

This role pays more than 52% of similar roles. Most pay $157,587–$229,106 — the shaded band above. At the midpoint, this role pays about $187k versus about $193k for comparable roles.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 223 open roles on FindRole.

Listed pay typically runs $121,900–$195,000 across 160 roles with salary data.

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View all roles at Broadcom

At a glance

TL;DR · RTL Integration Engineer

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The RTL integration Engineer will perform IP integration and IP test/debug mode verification at the SoC level. The daily responsibilities involve creating RTL designs, performing linting, and executing CDC and RDC analysis for both RTL and gates. This role also requires handling synthesis, palladium modeling, and STA support while utilizing strong debugging skills to resolve issues effectively. To succeed in this position, the candidate must possess extensive knowledge of implementation, synthesis, and timing issues alongside a strong understanding of UVM and SystemVerilog. The role involves performing gate-level simulation, zero-delay simulations, and SDF simulations. Technical proficiency with tools such as NCSim and VCS is required to navigate the technical challenges of SoC integration. This position focuses on solving complex hardware design problems within the semiconductor domain through rigorous verification and integration processes.

Skills

SystemVerilog UVM RTL Design Synthesis STA CDC RDC Gate-level Simulation SDF NCSim VCS Palladium Modeling Linting

What you'll do

  • Perform IP integration and IP test/debug mode verification at the SoC level.
  • Create RTL designs and perform linting for hardware components.
  • Execute CDC and RDC analysis for both RTL and gate-level designs.
  • Manage synthesis processes and provide Static Timing Analysis (STA) support.
  • Develop palladium modeling for design implementation.
  • Perform zero-delay and SDF simulations to identify and debug failures.
  • Conduct gate-level simulations (GLS) using tools like NCSim or VCS.

What we're looking for

  • Bachelor's degree required.
  • 12+ years of related experience.
  • Extensive knowledge of implementation, synthesis, and timing issues.
  • Strong understanding of UVM and SystemVerilog.
  • Experience in gate-level simulation (GLS) and debugging zero-delay and SDF simulations.
  • Familiarity with Clock Domain Crossing (CDC) analysis for both RTL and gate-level designs.
  • Experience with simulation tools such as NCSim and VCS (preferred).
  • Ability to work independently, adapt to new methodologies, and communicate effectively in a global team environment.

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