Digital Design RTL Engineer

Broadcom

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Quick summary

Work type
On-site
Location
Fort Collins, COSan Jose, CA
Salary
$121,900–$195,000 / yr
Employment
Full-time
Posted
74 days ago
Freshness
Confirmed live today
Closes
Jan 18, 2027
Nearby
99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $198k
This role $158k
$109k most similar roles pay here $243k

This role pays less than 83% of similar roles. Most pay $166,513–$229,100 — the shaded band above. At the midpoint, this role pays about $158k versus about $198k for comparable roles.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 223 open roles on FindRole.

Listed pay typically runs $121,900–$195,000 across 160 roles with salary data.

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View all roles at Broadcom

At a glance

TL;DR · Digital Design RTL Engineer

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As a Digital Design RTL Engineer, you will join the team to deliver high-quality SystemVerilog RTL for advanced process nodes at 5nm and below. You will operate with a high degree of autonomy, taking designs from initial specification through timing closure and physical design hand-off while collaborating cross-functionally with Architecture, Verification, and Physical Design teams to mitigate risks and meet project milestones. Your daily work involves PPA optimization, clock domain crossing (CDC) analysis, Reset Domain crossing (RDC), and implementing low-power design techniques. The role focuses on complex SoC integration involving specific memory and communication protocols such as LPDDR5/6, DDR4/5, high-speed SerDes, or HBM. You will utilize SystemVerilog to solve technical challenges in advanced semiconductor manufacturing, ensuring that all designs meet rigorous performance and power requirements within the specified advanced process nodes.

Skills

SystemVerilog RTL Design PPA Optimization Clock Domain Crossing (CDC) Reset Domain Crossing (RDC) Low-Power Design SoC Integration LPDDR5 DDR4 DDR5 SerDes HBM Timing Closure Physical Design

What you'll do

  • Deliver high-quality SystemVerilog RTL for advanced process nodes at 5nm and below.
  • Perform PPA optimization to improve power, performance, and area metrics.
  • Conduct clock domain crossing (CDC) and reset domain crossing (RDC) analysis.
  • Implement low-power design techniques within the RTL architecture.
  • Manage designs from initial specification through timing closure and physical design hand-off.
  • Mitigate technical risks to ensure project milestones are met on schedule.

What we're looking for

  • A BSEE degree is required.
  • An MSEE or PhD is preferred.
  • High proficiency in SystemVerilog is required.
  • Proven track record of delivering high-quality SystemVerilog RTL in advanced process nodes (5nm and below).
  • Deep understanding of PPA optimization, clock domain crossing (CDC) analysis, and Reset Domain crossing (RDC).
  • Experience with low-power design techniques.
  • 8+ years of industry experience is required.
  • Experience with SoC integration, LPDDR5/6, DDR4/5, high-speed SerDes, or HBM protocols is preferred.

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