RTL Design & Integration Engineer

Amd

Confirmed live today High trust

Quick summary

Work type
On-site
Location
San Jose, CA
Salary
$166,400–$249,600 / yr
Posted
66 days ago
Freshness
Confirmed live today
Closes
Aug 21, 2027
Nearby
99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $186k
This role $208k
$133k $262k
below market most similar roles pay here above market

This role pays more than 62% of similar roles. Most pay $152,175–$219,500 — the blue band above. At the midpoint, this role pays about $208k versus about $186k for comparable roles.

Based on 240 similar postings.

Employer

About Amd

AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors

Amd currently has 496 open roles on FindRole.

Listed pay typically runs $172,000–$258,000 across 496 roles with salary data.

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At a glance

TL;DR · RTL Design & Integration Engineer

Role Posting Log in to save

As an RTL Design & Integration Engineer within the FPGA Product development team, you will support the technical execution of Adaptive & Embedded Computing Group device programs from initial planning through productization. You will build early-stage RTL designs based on architecture intent, drive silicon and solution co-development, and enhance AI-driven infrastructure to accelerate IP integration. Your daily work involves collaborating with architects and software engineers to ensure PPA, cost, and schedule optimization. You will utilize Verilog, SystemVerilog, and scripting languages like Perl, Tcl, Python, and Shell. Technical requirements include expertise in VLSI design flows, including synthesis, floorplanning, P&R, and STA, alongside experience with Synopsys Design Compiler, Primetime, VCS, and Cadence Virtuoso. You will also support functional simulation and software quality checks.

Skills

RTL Design Verilog SystemVerilog FPGA VLSI UVM OVM Python Tcl Perl Shell Synopsys Design Compiler PrimeTime VCS Cadence Virtuoso Physical Design Synthesis P&R STA GDSII Functional Simulation

What you'll do

  • Execute technical development of AECG device programs from initial planning to productization.
  • Build early-stage RTL designs based on product and architecture intent.
  • Develop and enhance AI-driven infrastructure to accelerate IP integration and development timelines.
  • Apply data-driven methodologies to align engineering teams across next-generation products and technology nodes.
  • Support functional simulation and software quality checks to ensure robust verification coverage.
  • Utilize modern RTL design methodologies and advanced EDA tools to optimize PPA, cost, and schedule.
  • Script design automation using Perl, Tcl, Python, or Shell.

What we're looking for

  • Bachelor’s or Master’s in Computer Engineering or Electrical Engineering.
  • Background expertise in RTL design using Verilog or SystemVerilog (preferred).
  • Experience with digital and analog block implementation (preferred).
  • Understanding of VLSI design flow from RTL through Physical Design and GDSII (preferred).
  • Familiarity with floorplanning, synthesis, P&R, and STA (preferred).
  • Experience with EDA tools such as Synopsys Design Compiler, Primetime, VCS, or Cadence Virtuoso (preferred).
  • Knowledge of UVM/OVM verification, simulation environments, and debugging (preferred).
  • Proficiency in scripting using Perl, Tcl, Python, or Shell for design automation (preferred).

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