Senior RTL Engineer, Memory Centric Computing

Samsung Semiconductor

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
San Jose, CA
Salary
$138,000–$206,000 / yr
Posted
23 days ago
Freshness
Confirmed live yesterday
Nearby
99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $202k
This role $172k
$126k most similar roles pay here $254k

This role pays less than 82% of similar roles. Most pay $177,250–$226,350 — the shaded band above. At the midpoint, this role pays about $172k versus about $202k for comparable roles.

Based on 240 similar postings.

Employer

About Samsung Semiconductor

Samsung Semiconductor is the global semiconductor business unit of Samsung Electronics, designing and manufacturing memory chips, logic semiconductors, and foundry solutions for a broad range of applications.

Samsung Semiconductor currently has 49 open roles on FindRole.

Listed pay typically runs $163,000–$253,000 across 49 roles with salary data.

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At a glance

TL;DR · Senior RTL Engineer, Memory Centric Computing

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As a Senior RTL Engineer, Memory Centric Computing within the AGI Computing Lab, you will develop IP for memory centric computing systems to address complex system-level challenges posed by growing AI/ML workloads. You will be responsible for designing and developing test plans with verification engineers, troubleshooting hardware issues, and making critical design decisions regarding performance, power, area, thermal, and cost trade-offs. Your daily work involves optimizing IP through pipelining, parallelism, and data compression while ensuring high quality through rigorous validation. The role requires expertise in Verilog, System Verilog, and HLS to build components like Memory Controllers, NOC, and Interconnect IP. You will leverage a strong background in microarchitecture and computer architecture to solve problems related to memory, computing, and interconnect technologies specifically tailored for demanding AI/ML applications and scalable platform development.

Skills

Verilog System Verilog HLS RTL Microarchitecture Computer Architecture Memory Controller NoC Interconnect IP SoC Integration AI/ML Pipelining Data Compression

What you'll do

  • Develop IP for memory-centric computing systems using Verilog, System Verilog, and HLS.
  • Optimize IP for performance, power, and area through pipelining, parallelism, and data compression.
  • Collaborate with verification engineers to design and develop comprehensive test plans.
  • Make critical design decisions regarding trade-offs between performance, power, thermal, and cost.
  • Troubleshoot and debug hardware issues to ensure high quality through verification and validation.
  • Research and integrate emerging technologies in memory, computing, interconnects, and AI/ML workloads.
  • Communicate with stakeholders to ensure projects are delivered on time and within budget.

What we're looking for

  • Bachelor’s degree with 5+ years of experience, Master’s with 3+ years, or PhD with 0+ years of experience.
  • Strong background in microarchitecture and computer architecture.
  • 5+ years of experience in front-end design methodology involving RTL development for complex control and data path IPs.
  • Experience designing Memory Controller, NOC, Interconnect IP, and Memory Centric computing IP with SoC integration.
  • Experience with AI/ML workloads.
  • Ability to develop IP using Verilog, System Verilog, and HLS while optimizing for performance, power, and area.
  • Strong analytical, problem-solving, and communication skills.

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