Senior RTL Engineer, Memory Centric Computing

Samsung Semiconductor

Confirmed live today High trust

Quick summary

Work type
On-site
Location
San Jose, CA
Salary
$138,000–$206,000 / yr
Posted
69 days ago
Freshness
Confirmed live today
Nearby
99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $201k
This role $172k
$125k $256k
below market most similar roles pay here above market

This role pays less than 80% of similar roles. Most pay $177,250–$223,837 — the blue band above. At the midpoint, this role pays about $172k versus about $201k for comparable roles.

Based on 240 similar postings.

Employer

About Samsung Semiconductor

Samsung Semiconductor is the global semiconductor business unit of Samsung Electronics, designing and manufacturing memory chips, logic semiconductors, and foundry solutions for a broad range of applications.

Samsung Semiconductor currently has 36 open roles on FindRole.

Listed pay typically runs $163,000–$253,000 across 36 roles with salary data.

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At a glance

TL;DR · Senior RTL Engineer, Memory Centric Computing

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The Senior RTL Engineer, Memory Centric Computing joins the AGI Computing Lab to address complex system-level challenges posed by future AI/ML workloads. This role involves developing IP for memory centric computing systems while optimizing for performance, power, and area using techniques like pipelining, parallelism, and data compression. The engineer will utilize Verilog, System Verilog, and HLS to build complex control and data path IPs, including Memory Controllers, NOC, and Interconnect IP. Key responsibilities include collaborating with verification engineers on test plans, troubleshooting hardware issues, and making design trade-offs across thermal, cost, and performance metrics. The position requires a strong background in microarchitecture and computer architecture to solve the computational and memory requirements of demanding AI/ML applications in a scalable, energy-efficient manner.

Skills

Verilog System Verilog HLS RTL Microarchitecture Computer Architecture Memory Controller NoC Interconnect IP SOC Integration AI/ML Pipelining Data Compression Hardware Architecture

What you'll do

  • Develop IP for memory-centric computing systems using Verilog, System Verilog, and HLS.
  • Optimize IP for performance, power, and area using pipelining, parallelism, and data compression.
  • Design and develop test plans in collaboration with verification engineers.
  • Make design decisions regarding trade-offs between performance, power, thermal, and cost.
  • Troubleshoot and debug hardware issues to ensure design quality through verification and validation.
  • Research and contribute to new technologies in machine learning and hardware architecture.
  • Communicate with stakeholders to ensure systems are delivered on time and within budget.

What we're looking for

  • Bachelor’s with 5+ years, Master’s with 3+ years, or PhD with 0+ years of industry experience.
  • Strong background in microarchitecture and computer architecture.
  • 5+ years of experience in front-end design methodology involving RTL development for complex control and data path IPs.
  • Experience in designing Memory Controller, NOC, Interconnect IP.
  • Experience in Memory Centric computing IP and SOC integration.
  • Experience in AI/ML workloads.
  • Ability to develop IP for memory centric computing systems using Verilog, System Verilog, and HLS.
  • Ability to optimize IP for performance, power, and area using pipelining, parallelism, and data compression.

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