SerDes RTL Design Engineer

Amd

Confirmed live today High trust
Hybrid

Quick summary

Work type
Hybrid
Location
San Jose, CA
Salary
$166,400–$249,600 / yr
Posted
22 days ago
Freshness
Confirmed live today
Closes
Sep 12, 2027
Nearby
99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $199k
This role $208k
$138k most similar roles pay here $262k

This role pays more than 57% of similar roles. Most pay $168,500–$229,100 — the shaded band above. At the midpoint, this role pays about $208k versus about $199k for comparable roles.

Based on 240 similar postings.

Employer

About Amd

AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors

Amd currently has 512 open roles on FindRole.

Listed pay typically runs $166,400–$249,600 across 512 roles with salary data.

Most-posted roles

View all roles at Amd

At a glance

TL;DR · SerDes RTL Design Engineer

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The SerDes RTL Design Engineer joins the SerDes Technology team to develop high-performance, multi-protocol wireline transceivers in state-of-the-art CMOS processes. In this role, you will collaborate with system link architects to micro-architect cutting-edge high-speed SerDes PHY designs and perform RTL design for digital blocks including calibration loops, digital signal processing, and clock-data-recovery. Daily responsibilities include applying low power techniques, performing PPA analysis, running LINT/CDC/RDC tools, and conducting behavioral modeling of custom circuits. You will also support functional verification, debug designs, and manage static timing closure to ensure pre-tape out sign-off. The role requires proficiency in Verilog, SystemVerilog, and scripting languages like Python, Perl, or TCL. Candidates must possess expertise in logic design, synthesis flows, mixed-signal design, and high-speed I/O protocols such as PMA and PCS.

Skills

RTL Verilog System Verilog SerDes PMA PCS Python Perl TCL CMOS Static Timing Analysis LINT CDC RDC Digital Signal Processing Low Power Design Mixed Signal Design PPA Analysis

What you'll do

  • Micro-architect high-speed SerDes PHY designs in collaboration with system link architects.
  • Perform RTL design of digital blocks including calibration loops, DSP, and clock-data recovery.
  • Implement low power design techniques and perform PPA analysis.
  • Verify intended functionality using block-level test benches.
  • Execute design checker tools such as LINT, CDC, and RDC.
  • Create behavioral models of custom circuits using Verilog or SystemVerilog.
  • Support functional verification, debugging, and static timing closure.
  • Coordinate with physical design and validation teams for pre-tape out sign-off and silicon bring-up.

What we're looking for

  • Bachelor's or master's degree in electrical engineering, computer engineering, or a related field.
  • Proficiency in logic design concepts and RTL coding using Verilog/System Verilog (preferred).
  • Proficiency in micro-architecture and developing design specifications (preferred).
  • Proficiency with design checker tools and functional verification tools (preferred).
  • Knowledge of synthesis flow, static timing analysis, and low power design methodology (preferred).
  • Experience in design with multiple clock domains (preferred).
  • Experience in mixed signal design (preferred).
  • Experience with Python, Perl, TCL, or other scripting languages (preferred); experience with SerDes PHY and high-speed I/O protocols (preferred).

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