RTL Tools & Methodology Engineer

Amd

Confirmed live today High trust

Quick summary

Work type
On-site
Location
San Jose, CA
Salary
$141,760–$212,640 / yr
Posted
26 days ago
Freshness
Confirmed live today
Closes
Oct 1, 2027
Nearby
99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $199k
This role $177k
$130k $254k
below market most similar roles pay here above market

This role pays less than 67% of similar roles. Most pay $168,500–$229,100 — the blue band above. At the midpoint, this role pays about $177k versus about $199k for comparable roles.

Based on 240 similar postings.

Employer

About Amd

AMD (Advanced Micro Devices) is a semiconductor company that develops high-performance processors, graphics cards, and adaptive computing solutions for gaming, data centers, and embedded markets. Industry: Semiconductors

Amd currently has 496 open roles on FindRole.

Listed pay typically runs $172,000–$258,000 across 496 roles with salary data.

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At a glance

TL;DR · RTL Tools & Methodology Engineer

Role Posting Log in to save

As an RTL Tools & Methodology Engineer, you will join the RTL Design Methodology team as a Hardware Development Engineer to support the development of next-generation FPGA products. You will work closely with RTL designers and verification engineers to define and improve methodologies and tools that enable high-quality RTL design across the engineering organization. Your daily responsibilities include supporting the deployment of front-end design and static verification flows, driving continuous improvements in areas such as Lint, CDC, formal equivalence, and low-power verification, and leveraging corporate AI systems to streamline workflows. The role requires proficiency in logic design and static verification using SystemVerilog, Verilog, or VHDL, along with programming skills in Perl, Python, and TCL to solve complex technical problems within the FPGA development domain.

Skills

RTL Design SystemVerilog Verilog VHDL Python Perl TCL Static Verification Lint CDC Formal Equivalence Low-Power Verification FPGA Logic Design

What you'll do

  • Develop and improve methodologies and tools for high-quality RTL design.
  • Support the deployment of front-end design and static verification flows.
  • Drive continuous improvements in Lint, CDC, formal equivalence, and low-power verification.
  • Ensure the production of robust, high-quality silicon for next-generation FPGA products.
  • Leverage corporate AI systems to increase productivity and streamline engineering workflows.
  • Collaborate with design and verification teams to improve engineering processes.

What we're looking for

  • Bachelor's degree in Electrical or Computer Engineering.
  • Master's or PhD degree (preferred).
  • Experience in logic design and static verification using SystemVerilog, Verilog, or VHDL (preferred).
  • Strong background in RTL/logic design (preferred).
  • Programming skills in Perl, Python, and TCL (preferred).

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