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C++ C Linux Yocto OpenBMC ZephyrOS x86 ARM I2C PMBus AVSbus MDIO PCIe SPI USB SERDES Redfish DMTF MCTP PLDM SPDM Secure Boot u-boot Root of Trust NIC +20 more Show less

C++ C Linux Yocto OpenBMC ZephyrOS x86 ARM Device Drivers I2C PMBus AVSbus MDIO PCIe SPI USB SERDES Redfish DMTF MCTP PLDM SPDM Secure Boot u-boot Root of Trust Networking +21 more Show less

EE Hardware Design BOM Creation Board Design Validation ASIC SerDes Manufacturing Compliance Safety Precision Scopes Analyzers +6 more Show less

C++ C Linux Yocto OpenBMC ZephyrOS x86 ARM I2C PMBus AVSbus MDIO PCIe SPI USB SERDES Redfish DMTF MCTP PLDM SPDM Secure Boot u-boot Root of Trust NIC +20 more Show less

EE Hardware Design BOM Creation Board Design Validation ASIC SerDes Manufacturing Compliance Safety 2.5D +5 more Show less

EE Hardware Design BOM Creation Board Design ASIC SerDes Validation Precision Scopes Analyzers 2.5D 3D Memories Manufacturing +6 more Show less

C++ C Linux Yocto ZephyrOS OpenBMC x86 ARM I2C PMBus AVSbus MDIO PCIe SPI USB SERDES Redfish DMTF MCTP PLDM SPDM Secure Boot u-boot Root of Trust NIC +20 more Show less

Silicon Photonics Semiconductor Characterization Failure Analysis JMP Python R MATLAB Design for Reliability Design for Test Statistical Analysis IC Packaging Wafer Fabrication Fiber Optics Change Management PPQ Database Development +11 more Show less

C C++ Python SAI SONiC FBOSS ASIC SDK L2 L3 ACL QoS SRv6 Telemetry GitHub Jenkins Gerrit GNU tools +12 more Show less

EE Hardware Design BOM Creation Board Design ASIC SerDes Validation Manufacturing Compliance Safety Precision Scopes Analyzers +6 more Show less

Physical Design Netlist to GDSII Floorplanning Design Partitioning Block Pin Assignment PnR Timing Closure Physical Verification IR/EM Analysis Tcl Perl Python Low-power IC Design +8 more Show less

Verilog VHDL Python Perl C RTL Synthesis STA CDC Lint HDL ASIC DSP High-level Synthesis Unix Digital Signal Processing Error Correction Code Design for Test Design for Manufacturing +14 more Show less

SystemVerilog UVM Verilog C++ C ASIC Verification FPGA Ethernet PCIe Networking Protocols Object-Oriented Programming ASIC Design Flow +7 more Show less

ASIC Design RTL Synthesis Verilog TCL Perl Synopsys Design Compiler Cadence RTL Compiler Formal Verification Synopsys Formality Cadence Conformal Spyglass Lint DFT Scan Methodology Git SVN Timing Analysis Power Analysis +12 more Show less

ASIC Design RTL Synthesis Verilog TCL Perl Synopsys Design Compiler Cadence RTL Compiler Formal Verification Synopsys Formality Cadence Conformal Spyglass Lint DFT Scan Methodology Git SVN Timing Analysis Power Analysis +12 more Show less

Advanced Packaging System in Package Wafer Foundry IC Design EFA PFA Stress Simulation Power Delivery Optical Communication R&D Product Development +6 more Show less

CoWoS 2.5D 3D Integration Cadence Innovus Synopsys 3DIC Compiler Mentor Graphics (Calibre Python Tcl SKILL TSV Design Signal Integrity Power Integrity Thermal Analysis 3DBlox Semiconductor Fabrication EDA Tools Physical Verification +12 more Show less

SystemVerilog UVM C RTL ATE Design Verification Testbenches Checkers Transactors Networking Switching Gatesim +7 more Show less

SystemVerilog UVM C RTL GateSim ATE Design Verification Testbenches Checkers Transactors Networking Switching +7 more Show less