R&D Engineer IC Design IV

Broadcom

Confirmed live 2 days ago High trust

Quick summary

Work type
On-site
Location
San Jose, CAAustin, TX
Salary
$121,900–$195,000 / yr
Posted
71 days ago
Freshness
Confirmed live 2 days ago
Closes
Dec 28, 2026
Nearby
99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $190k
This role $158k
$109k most similar roles pay here $244k

This role pays less than 77% of similar roles. Most pay $162,000–$217,500 — the shaded band above. At the midpoint, this role pays about $158k versus about $190k for comparable roles.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 119 open roles on FindRole.

Listed pay typically runs $121,900–$195,000 across 105 roles with salary data.

Most-posted roles

View all roles at Broadcom

At a glance

TL;DR · R&D Engineer IC Design IV

Role Posting Log in to save

As an R&D Engineer IC Design 4, you will join the team to perform front end design and verification of design blocks for specific cores. Your daily responsibilities include architecture definition, logic design, synthesis, constraint development, and design verification through simulation and formal verification. You will also analyze timing from physical implementations and develop logic blocks based on systems requirements documents while debugging designs using Verilog simulation. The role requires expertise in the complete ASIC implementation flow, including RTL synthesis and timing closure. Essential technical skills include proficiency with TCL and Perl scripting, Synopsys Design Compiler or Cadence RTL compiler, Primetime for high frequency designs, and Liberty LIB models. You will also utilize tools like Spyglass Lint, perform power analysis of netlists, and manage version control using SVN or Git.

Skills

ASIC Verilog Synthesis Timing Analysis TCL Perl Synopsys Design Compiler Cadence RTL Compiler Primetime Formal Verification Synopsys Formality Cadence Conformal Spyglass Lint DFT Scan Methodology Git SVN

What you'll do

  • Perform front end design and verification of design blocks for core components.
  • Define architecture, perform logic design, and develop constraints for hardware blocks.
  • Execute synthesis using Synopsys Design Compiler or Cadence RTL compiler.
  • Conduct timing analysis and closure for high-frequency designs using Primetime.
  • Verify designs through Verilog simulation, formal verification, and Spyglass Lint.
  • Perform power analysis on RTL and gate-level netlists.
  • Develop TCL and Perl scripts to support the design flow.
  • Manage version control of designs using tools like SVN or Git.

What we're looking for

  • BS/MS in Electrical or Computer Engineering or equivalent.
  • Bachelor's degree with 8+ years of related experience.
  • Master's degree with 6+ years of related experience.
  • Experience with complete ASIC or standard product implementation flow from RTL synthesis to timing analysis and closure.
  • Proficiency in TCL/Perl scripting.
  • Synthesis experience with Synopsys Design Compiler, DC topo, or Cadence RTL compiler.
  • Timing analysis experience with Primetime for high frequency designs and advanced technology nodes.
  • Experience with formal verification tools like Synopsys Formality or Cadence Conformal.

Related searches

More R&D Engineer IC Design 4 jobs R&D Engineer IC Design 4 jobs in San Jose All jobs at Broadcom

More like this

Similar roles

R&D Engineer IC Design IV

Broadcom

Austin, TX +1 45 days ago $121,900–$195,000
ASIC Verilog Synthesis Timing Analysis TCL Perl Synopsys Design Compiler Cadence RTL Compiler Primetime Liberty LIB Formal Verification Synopsys Formality Cadence Conformal Spyglass Lint DFT Scan Methodology Git SVN
8+ yrs exp
Save

R&D Engineer IC Design V

Broadcom

San Jose, CA 36 days ago $143,800–$230,000
SystemVerilog UVM Verilog C++ C ASIC Verification FPGA Ethernet PCIe Routing Switching Object-Oriented Programming Simulation Tape-out
8+ yrs exp
Save

R&D IC Design Engineer

Broadcom

Irvine, CA +1 14 days ago
Verilog VHDL RTL ASIC STA CDC Lint Synthesis Python Perl C Unix High-Level Synthesis DSP Ethernet OTN Silicon Debugging Design for Test Design for Manufacturing
10+ yrs exp
Save

Principal IC Design Engineer

Broadcom

Broomfield, CO +1 2 days ago $129,400–$207,000
Verilog VHDL SystemVerilog SOC Architecture DRAM Interface Design Synthesis Formal Verification Timing Closure Signal Integrity Physical Implementation HDL
10+ yrs exp
Save

RF/Analog IC Design Engineer

Qualcomm

Santa Clara, CA 50 days ago $168,600–$252,800
RFIC ASIC Design Cadence Virtuoso ADS LNA PLL 4G 5G WLAN GPS Electro Magnetic simulation post silicon characterization Signal Processing Transistor-level Design
3+ yrs exp
Save

Physical IC Design Engineer

Broadcom

San Jose, CA 84 days ago $143,800–$230,000
Physical Design RTL to Tape-out Synthesis Timing Closure EM/IR Analysis Place and Route Clock Tree Synthesis Floor-planning Layout TCL Perl EDA Tools ASIC Machine Learning PCIe
10+ yrs exp
Save