R&D Engineer IC Design 4

Broadcom

Confirmed live today High trust

Quick summary

Work type: On-site
Location: Austin, TXSan Jose, CA
Salary: $121,900–$195,000 / yr
Employment: Full-time
Posted: 91 days ago
Freshness: Confirmed live today
Closes: Jan 24, 2027
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $198k

This role $158k

$108k $251k

below market most similar roles pay here above market

This role pays less than 82% of similar roles. Most pay $167,500–$227,900 — the blue band above. At the midpoint, this role pays about $158k versus about $198k for comparable roles.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 280 open roles on FindRole.

Listed pay typically runs $121,900–$195,000 across 169 roles with salary data.

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At a glance

TL;DR · R&D Engineer IC Design 4

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The R&D Engineer IC Design 4 will join the team to handle the front end design and verification of design blocks for specific cores. The role involves architecture definition, logic design, synthesis, and constraint development based on systems requirements documents. Key responsibilities include design verification through simulation and formal verification, along with analyzing timing from physical implementations. The candidate will utilize Verilog simulation, TCL, and Perl scripting to debug designs. Required technical expertise includes Synopsys Design Compiler, Cadence RTL compiler, and Primetime for high frequency designs. Proficiency in liberty LIB models, Synopsys Formality, Cadence Conformal, Spyglass Lint, and power analysis of RTL and gate level netlists is necessary. Experience with DFT, scan methodology, and version control systems like svn or git is required.

Skills

ASIC Design RTL Synthesis Verilog TCL Perl Synopsys Design Compiler Cadence RTL Compiler Formal Verification Synopsys Formality Cadence Conformal Spyglass Lint DFT Scan Methodology Git SVN Timing Analysis Power Analysis

What you'll do

Perform front end design and verification of design blocks for cores.
Define architecture and develop logic designs from systems requirements documents.
Execute logic synthesis and develop timing constraints for designs.
Conduct design verification through simulation and formal verification methods.
Analyze timing from physical implementations using Primetime for high frequency designs.
Perform power analysis of RTL and gate level netlists.
Utilize TCL and Perl scripting for design tool automation.
Execute linting and formal verification using Spyglass and Formality.

What we're looking for

BS/MS in Electrical or Computer Engineering or equivalent.
Bachelors and 8+ years of related experience; or Masters degree and 6+ years of related experience.
Experience with complete ASIC or standard product implementation flow from RTL synthesis to timing analysis and closure.
Proficiency with TCL/Perl scripting.
Synthesis experience with either Synopsys Design Compiler/DC topo or Cadence RTL compiler.
Timing analysis experience with Primetime for high frequency designs and advanced technology nodes/libraries.
Experience with Formal verification (Synopsys Formality / Cadence Conformal), Spyglass Lint, and power analysis of RTL and gate level netlists.
Familiarity with DFT (design for test) and scan methodology, and version control (svn, git, etc).