R&D Engineer IC Design IV

Broadcom

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
Austin, TXSan Jose, CA
Salary
$121,900–$195,000 / yr
Posted
45 days ago
Freshness
Confirmed live yesterday
Closes
Jan 24, 2027
Nearby
99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $190k
This role $158k
$109k most similar roles pay here $244k

This role pays less than 77% of similar roles. Most pay $162,000–$217,500 — the shaded band above. At the midpoint, this role pays about $158k versus about $190k for comparable roles.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 119 open roles on FindRole.

Listed pay typically runs $121,900–$195,000 across 105 roles with salary data.

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At a glance

TL;DR · R&D Engineer IC Design IV

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As an R&D Engineer IC Design 4, you will join the team to perform front end design and verification of design blocks for specific cores. Your daily responsibilities include architecture definition, logic design, synthesis, constraint development, and analyzing timing from physical implementation. You will translate systems requirements documents into logic blocks while performing simulation and debugging using Verilog. The role requires expertise in the complete ASIC design and implementation flow, including RTL synthesis and timing closure. Essential technical skills include proficiency with TCL and Perl scripting, Synopsys Design Compiler or Cadence RTL compiler, Primetime for high frequency designs, and Liberty LIB models. You will also utilize tools like Synopsys Formality, Cadence Conformal, Spyglass Lint, and version control systems such as SVN or Git to ensure robust design quality.

Skills

ASIC Verilog Synthesis Timing Analysis TCL Perl Synopsys Design Compiler Cadence RTL Compiler Primetime Liberty LIB Formal Verification Synopsys Formality Cadence Conformal Spyglass Lint DFT Scan Methodology Git SVN

What you'll do

  • Perform front end design and verification of design blocks for core components.
  • Define architecture, perform logic design, and develop constraints for integrated circuits.
  • Execute synthesis using tools like Synopsys Design Compiler or Cadence RTL compiler.
  • Conduct timing analysis and closure for high frequency designs using Primetime.
  • Verify designs through Verilog simulation, formal verification, and Spyglass Linting.
  • Perform power analysis of RTL and gate level netlists.
  • Develop TCL and Perl scripts to support the ASIC design and implementation flow.
  • Manage version control for design files using systems like SVN or Git.

What we're looking for

  • BS/MS in Electrical or Computer Engineering or equivalent.
  • Bachelor's degree with 8+ years of related experience or a Master's degree with 6+ years of related experience.
  • Experience with complete ASIC or standard product implementation flow from RTL synthesis to timing analysis and closure.
  • Proficiency in TCL and Perl scripting.
  • Synthesis experience with Synopsys Design Compiler/DC topo or Cadence RTL compiler.
  • Timing analysis experience with Primetime for high frequency designs and advanced technology nodes.
  • Experience with formal verification tools like Synopsys Formality or Cadence Conformal.
  • Familiarity with DFT, scan methodology, power analysis, and version control systems.

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