R&D IC Design Engineer

Broadcom

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Quick summary

Work type: On-site
Location: Irvine, CASan Jose, CA
Salary: $121,900–$195,000 / yr
Employment: Full-time
Posted: 31 days ago
Freshness: Confirmed live today
Closes: Feb 20, 2027
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $202k

This role $158k

$106k most similar roles pay here $267k

This role pays less than 79% of similar roles. Most pay $162,000–$241,750 — the shaded band above. At the midpoint, this role pays about $158k versus about $202k for comparable roles.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 172 open roles on FindRole.

Listed pay typically runs $121,900–$195,000 across 125 roles with salary data.

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At a glance

TL;DR · R&D IC Design Engineer

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The R&D IC Design Engineer joins the physical design team to implement chips from netlist to GDSii while managing various stages of the design flow. This role involves critical tasks such as floorplanning, design partitioning, block pin assignment, and performing block PnR, timing closure, and physical verification. The engineer will also conduct block IR/EM analysis and is expected to write scripts in Tcl, Perl, or Python to automate the physical design flow and increase overall efficiency. Candidates should possess expertise in low-power IC design and have a strong knowledge of physical verification using Mentor’s Calibre tool. This position focuses on solving complex integrated circuit challenges by navigating technical requirements throughout the chip development process, ensuring that all components meet specific timing and power constraints within the established hardware engineering framework.

Skills

Physical Design GDSII Floorplanning PnR Timing Closure IR/EM Analysis Tcl Perl Python Low-power IC Design Physical Verification

What you'll do

Implement chips from netlist to GDSII while managing all stages of the design flow.
Execute floorplanning, design partitioning, and block pin assignment.
Perform Place and Route (PnR) and achieve timing closure for blocks.
Conduct physical verification using Mentor’s Calibre tool.
Perform IR/EM analysis at both the block and chip levels.
Develop scripts in Tcl, Perl, or Python to automate the physical design flow.

What we're looking for

Bachelor's degree and 8+ years of related experience or Master's degree with 6+ years of experience.
Experience implementing chips from netlist to GDSii with knowledge of technology elements and design flow.
Proficiency in floorplanning, design partitioning, and block pin assignment.
Ability to perform block PnR, timing closure, and physical verification.
Ability to perform block IR/EM analysis.
Familiarity with scripting languages such as Tcl, Perl, and Python for automation.
Experience with chip level IR/EM analysis (preferred).
Expertise in low-power IC design (preferred).

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