R&D Engineer IC Design V

Broadcom

Confirmed live yesterday High trust

Quick summary

Work type: On-site
Location: San Jose, CA
Salary: $143,800–$230,000 / yr
Posted: 36 days ago
Freshness: Confirmed live yesterday
Closes: Jan 22, 2027
Nearby: 99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $192k

This role $187k

$132k most similar roles pay here $255k

This role pays less than 55% of similar roles. Most pay $162,000–$222,000 — the shaded band above. At the midpoint, this role pays about $187k versus about $192k for comparable roles.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 119 open roles on FindRole.

Listed pay typically runs $121,900–$195,000 across 105 roles with salary data.

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At a glance

TL;DR · R&D Engineer IC Design V

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As an R&D Engineer IC Design 5, you will join the ASIC system-level verification team to develop complex verification environments and create comprehensive test plans for high-performance network switch ASICs and FPGAs. You will be responsible for hands-on implementation across all aspects of ASIC verification while collaborating with system architects and design engineers to achieve full verification closure. The role requires a proven track record of completing multiple successful ASIC design cycles from initial concept through production. You must possess strong working knowledge of object-oriented programming, modern ASIC verification flows like UVM and SystemVerilog, and mastery of Verilog for simulation. Additionally, you will utilize C/C++ and apply expertise in networking protocols such as Ethernet, PCIe, and routing or switching to solve technical challenges within the high-performance networking domain.

Skills

SystemVerilog UVM Verilog C++ C ASIC Verification FPGA Ethernet PCIe Routing Switching Object-Oriented Programming Simulation Tape-out

What you'll do

Develop complex verification environments for high-performance network switch ASICs and FPGAs.
Create comprehensive test plans to ensure full verification closure.
Implement hands-on verification across all stages of the ASIC design cycle.
Architect testbenches specifically tailored for networking applications.
Verify hardware designs against specifications using SystemVerilog and UVM methodologies.
Execute multiple ASIC tape-out cycles from initial concept through production.
Document technical specifications and communicate project status to cross-functional teams.

What we're looking for

8+ years of ASIC design/verification experience.
Bachelor's degree in Engineering.
Proficiency in Verilog for simulation and mastery of deep sub-micron ASIC design flows.
Hands-on experience with C/C++ and object-oriented programming (OOP).
Strong working knowledge of modern ASIC verification flows, including UVM and SystemVerilog.
Proven track record of completing multiple ASIC tape-outs from initial concept through full production.
Experience with networking protocols such as Ethernet, PCIe, routing, and switching.
Fluency in technical and business English for documentation and cross-functional collaboration.

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