R&D Engineer IC Design 5

Broadcom

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Quick summary

Work type
On-site
Location
San Jose, CA
Salary
$143,800–$230,000 / yr
Employment
Full-time
Posted
82 days ago
Freshness
Confirmed live today
Closes
Jan 22, 2027
Nearby
99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $200k
This role $187k
$131k $268k
below market most similar roles pay here above market

This role pays less than 55% of similar roles. Most pay $168,425–$231,275 — the blue band above. At the midpoint, this role pays about $187k versus about $200k for comparable roles.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 280 open roles on FindRole.

Listed pay typically runs $121,900–$195,000 across 169 roles with salary data.

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At a glance

TL;DR · R&D Engineer IC Design 5

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The R&D Engineer IC Design 5 will join the ASIC system-level verification team to develop complex verification environments and create comprehensive test plans. This role involves hands-on implementation across every aspect of ASIC verification, specifically focusing on verifying high-performance network switch ASICs and FPGAs. The successful candidate will collaborate with system architects and design engineers to achieve full verification closure. Key technical requirements include mastery of Verilog for simulation, hands-on experience with C/C++, and strong working knowledge of object-oriented programming and modern ASIC verification flows like UVM/SystemVerilog. The work centers on deep sub-micron technologies and networking protocols, including Ethernet, PCIe, and routing or switching. Candidates must have a proven track record of completing multiple ASIC tape-outs from initial concept through full production.

Skills

SystemVerilog UVM Verilog C++ C ASIC Verification FPGA Ethernet PCIe Networking Protocols Object-Oriented Programming ASIC Design Flow

What you'll do

  • Develop complex verification environments for high-performance network switch ASICs and FPGAs.
  • Create comprehensive test plans to ensure full verification closure.
  • Architect testbenches for networking protocols like Ethernet and PCIe.
  • Implement verification flows using SystemVerilog and UVM.
  • Execute hands-on verification across all aspects of the ASIC design cycle.
  • Manage projects from initial concept through full production and tape-out.
  • Write technical documentation and communicate design status to cross-functional teams.

What we're looking for

  • 8+ years of ASIC design/verification experience.
  • Bachelor's degree in Engineering.
  • Complete mastery of Verilog for simulation.
  • Strong working knowledge of object-oriented programming (OOP) and modern ASIC verification flows like UVM/SystemVerilog.
  • Hands-on experience with C/C++.
  • Experience with networking protocols such as Ethernet, PCIe, routing, or switching (preferred).
  • Must have completed multiple ASIC tape-outs, including at least one project from initial concept through full production.
  • Fully comfortable with technical and business English for documentation and cross-functional collaboration.

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