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Physical Design Timing Engineer (STA)

Broadcom

San Jose, CA 15 days ago $141,300$226,000
Actively hiring Verified listing Competitive pay
Tcl Python Perl Cadence Synopsys ASIC STA SDC On-Chip_Variation Signal_Integrity IR-drop_aware_STA MMMC_Analysis ECOs RTL Physical_Design DFT Power_Performance_Area_Tradeoffs EDA_Tools

Physical Design Engineer

Broadcom

San Jose, CA 40 days ago $120,000$192,000
Actively hiring Verified listing Competitive pay
Python Tcl Perl Hierarchical_design_planning Power_grid_design Structured_clocks Top_level_pipeline_placement Custom_routes Bump_planning RDL_routes Multi_voltage_domain_designs DRC LVS EMIR Chiplet SerDes HBM DDR Switch_Fabric Arbiter

Physical Design Engineer

Broadcom

San Jose, CA 108 days ago $141,300$226,000
Actively hiring Verified listing Above market
Python Tcl Perl DV DRC LVS EMIR bump_planning RDL_routes multi_voltage_domain_design hierarchical_design_planning power_grid_design structured_clocks top_level_pipeline_placement custom_routes package_team_collaboration design_teams_collaboration methodology_teams_collaboration