This role pays less than
71%
of similar roles. Most pay
$162,000–$217,500
— the shaded band above.
At the midpoint, this role pays about
$164k
versus about
$190k
for comparable roles.
Based on 240 similar postings.
Employer
About Cisco
Cisco Systems is the world''s leading networking technology company, designing and manufacturing networking hardware, telecommunications equipment, and cybersecurity solutions for businesses and governments. Industry: Networking Technology & Cybersecurity
Cisco currently has
240 open roles
on FindRole.
Listed pay typically runs
$167,700–$245,000
across 188 roles with salary data.
As an ASIC Physical Design Engineer II on the Silicon One team, you will drive the RTL-to-GDSII implementation flow for advanced semiconductor nodes ranging from sub-16nm to 3nm. You will be responsible for executing hierarchical floor planning, place and route, clock and power distribution, and timing convergence strategies for high-performance networking chips. Your daily work involves performing static timing analysis, managing timing ECO strategies, and identifying improvements in backend design flows and methodologies. To succeed, you must possess skills in scripting languages like Python, Tcl, or Perl, along with experience using industry-standard EDA tools such as Cadence Innovus, Synopsys ICC2, Design Compiler, PrimeTime, or Mentor Calibre. You will collaborate with RTL, DFT, and EDA teams to solve complex technical challenges within the hardware platforms powering core switching, routing, and wireless products.
Drive RTL-to-GDSII implementation for advanced semiconductor nodes ranging from sub-16nm to 3nm.
Execute hierarchical floor planning, place and route, and clock and power distribution strategies.
Perform static timing analysis (STA) and manage multi-mode/multi-corner design sign-offs.
Develop automated scripts within STA tools to improve design flow efficiency.
Manage timing ECO strategies using industry-standard tools like Tweaker or PrimeTime.
Identify and resolve quality and efficiency gaps in backend design flows and methodologies.
Collaborate with RTL, DFT, and EDA vendors to optimize implementation processes.
What we're looking for
Candidates must have a Master's degree with 0 years of experience or a Bachelor's degree with 2 years of experience in ASIC Physical Design or related fields.
Foundational knowledge of ASIC physical design and implementation flows from academic projects, internships, or coursework is required.
Required understanding of physical design concepts including floor planning, clock tree synthesis, power distribution, and I/O planning.
Required exposure to the physical design lifecycle, including logic synthesis, placement, routing, and basic timing closure.
Proficiency in scripting languages such as Python, Tcl, or Perl for task automation and data analysis (preferred).
Hands-on experience with industry-standard EDA tools like Cadence Innovus, Synopsys ICC2, or Synopsys Design Compiler (preferred).
Familiarity with physical verification processes using tools such as Mentor Calibre or Synopsys ICV (preferred).
Exposure to static timing analysis concepts and tools, such as PrimeTime (preferred).