Physical Design Engineer

Broadcom

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Quick summary

Work type: On-site
Location: Colorado Springs, COSan Jose, CA
Salary: $121,900–$195,000 / yr
Employment: Full-time
Posted: 7 days ago
Freshness: Confirmed live today
Closes: Mar 27, 2027
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $205k

This role $158k

$106k most similar roles pay here $271k

This role pays less than 85% of similar roles. Most pay $168,500–$241,750 — the shaded band above. At the midpoint, this role pays about $158k versus about $205k for comparable roles.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 224 open roles on FindRole.

Listed pay typically runs $121,900–$195,000 across 161 roles with salary data.

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At a glance

TL;DR · Physical Design Engineer

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The Physical Design Engineer joins the Data Center Solutions Group to support next-generation AI/ML ecosystems through PCIe Switch Products and Enterprise Storage Products. This role involves managing the full physical design cycle from RTL to silicon tape-out, ensuring high performance for large-scale infrastructure. Key responsibilities include executing synthesis, physical verification, and timing closure using various strategies. The engineer will perform top-level STA, EM/IR analysis, floorplanning, and layout while developing flow methodologies. They will also manage custom clock trees with focus on insertion reduction and skew balancing. To succeed, the candidate must possess proficiency in TCL and PERL scripting alongside experience with related EDA tools. This position requires a deep understanding of physical design aspects to solve complex hardware challenges within the data center and storage product domains.

What does a Physical Design Engineer earn in California?

Median $184362 from 32 postings across 9 companies.

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Skills

Physical Design RTL to Tape-out Synthesis Timing Closure STA EM/IR Analysis Place and Route Clock Tree Synthesis Floorplanning Layout TCL Perl EDA Tools

What you'll do

Execute the full physical design cycle from RTL to silicon tape-out.
Perform synthesis, physical verification, and timing closure using various strategies.
Conduct top-level Static Timing Analysis (STA), EM, and IR analysis.
Manage floorplanning and layout for complex IC designs.
Implement custom clock tree synthesis including insertion reduction and skew balancing.
Develop internal flows and methodologies for the physical design process.
Write TCL and PERL scripts to automate tasks within EDA tools.

What we're looking for

Bachelor's degree in Electrical Engineering or Electronics Engineering.
8+ years of relevant experience.
Expertise in all Physical Design aspects from RTL to silicon tape-out.
Proficiency in TCL and PERL scripting for related EDA tools.
Experience with Synthesis, Physical Verification, and Timing Closure.
Excellent verbal and written communication skills.
In-depth experience in top-level STA EM/IR Analysis, Place and Route, and Clock Tree Synthesis (preferred).
In-depth experience in top-level floorplanning Flow and Methodology Development (preferred).

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