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UVM SystemVerilog C++ ASIC Verification SoC Verification HBM DDR UCIe Memory DFT CXL AI Accelerators +6 more Show less

Photonic Integrated Circuits Silicon Photonics Python MATLAB Ansys Lumerical Luceda IPKISS COMSOL Multiphysics Synopsys OptSim OptoCompiler Cadence Virtuoso Optical Spectrum Analyzers Vector Network Analyzers Oscilloscopes Data Analysis Automated Workflows Semiconductor Fabrication +11 more Show less

Serdes mixed signal CMOS LVS DRC Cadence Spectre Totem EMX Python Matlab UCIe PCIe USB PLL ADC DAC Ethernet +13 more Show less

System Verilog UVM OVM C C++ Perl SystemC RTL Verification ASIC Design FPGA Emulators DSP Scripting Coverage Assertions +10 more Show less

FPGA Verilog VHDL Python Tcl Ethernet PCIe I2C SPI Schematic Capture Hardware Bring-up Signal Integrity ASIC DFT +9 more Show less

RTL-to-GDSII ASIC Physical Design Static Timing Analysis (STA) Floor Planning Place and Route Clock Tree Synthesis Power Distribution Python Tcl Perl Cadence Innovus Synopsys ICC2 Synopsys Design Compiler Mentor Calibre Synopsys ICV PrimeTime DRC LVS +13 more Show less

Flip-chip BGA SerDes Signal Integrity Power Integrity Cadence APD Allegro Package Designer Cadence SKILL HBM DDR5 RF/Microwave Layout Automation Process Development +8 more Show less

Mixed-Signal Design Matlab SPICE FinFET ADC DAC PLL RF Silicon Photonics Analog Front-End Clock Distribution SAR-ADC +7 more Show less

Layout Design Timing Closure LVS DRC ERC Place and Route Standard Cell Development +2 more Show less

Photonic System Modeling SystemVerilog Python Julia Lumerical VPIphotonics OptiSystem COMSOL Multi-physics Modeling Signal Integrity SerDes DSP Algorithms Time-domain Simulation High-speed Link Characterization Data Processing +10 more Show less

Physical Design RTL to Tape-out Synthesis Timing Closure STA EM/IR Analysis Place and Route Clock Tree Synthesis Floorplanning Layout TCL Perl EDA Tools IC Design +9 more Show less

Physical Design RTL to Tape-out Synthesis Timing Closure STA EM/IR Analysis Place and Route Clock Tree Synthesis Floorplanning Layout TCL Perl EDA Tools +8 more Show less

Verilog SystemVerilog RTL Design PCIe CXL AMBA Micro-architecture Timing Closure Low-power Design Emulation Firmware Digital IC Design +7 more Show less

Physical Design RTL to Tape-out Synthesis Timing Closure STA EM/IR Analysis Place and Route Clock Tree Synthesis Floorplanning Layout TCL Perl EDA Tools +8 more Show less

Physical Design RTL to Tape-out Synthesis Physical Verification Timing Closure STA EM/IR Analysis Place and Route Clock Tree Synthesis Floorplanning Layout TCL Perl EDA Tools +9 more Show less

Verilog SystemVerilog UVM Python Tcl Perl Shell DFT STA ASIC SoC FPGA Synopsys Cadence VCS PrimeTime GDS HBM PCIe SerDes +15 more Show less

FPGA SystemVerilog Verilog Vivado Vitis Synopsys HAPS Cadence Protium SoC PCIe DDR Ethernet USB HBM AXI ACE CHI RTL CDC Analysis Floorplanning Timing Closure +15 more Show less

Cadence Virtuoso Analog Artist MATLAB SPICE Bandgap Layout Post-layout Extraction Silicon Bring-Up ATE Mixed-Signal Design +5 more Show less

Mixed-Signal Design Cadence Virtuoso MATLAB SPICE Bandgap High-Speed I/O Power Management Automatic Test Equipment (ATE) +3 more Show less

UVM System Verilog Formal Verification Assertion-Based Verification Synopsys VCS Cadence Xcelium JasperGold Questa Formal Gate-Level Simulation Power-Aware Verification DDR5 LPDDR6 HBM4 Network-on-Chip NoC VLSI Silicon Debug +12 more Show less