Principal Engineer, ASIC Design Verification

Samsung Semiconductor

Confirmed live today High trust

Quick summary

Work type: On-site
Location: San Jose, CAFolsom, CA
Salary: $219,000–$351,000 / yr
Posted: 2 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $198k

This role $285k

$126k most similar roles pay here $375k

This role pays more than 99% of similar roles. Most pay $168,200–$227,300 — the shaded band above. At the midpoint, this role pays about $285k versus about $198k for comparable roles.

Based on 240 similar postings.

Employer

About Samsung Semiconductor

Samsung Semiconductor is the global semiconductor business unit of Samsung Electronics, designing and manufacturing memory chips, logic semiconductors, and foundry solutions for a broad range of applications.

Samsung Semiconductor currently has 37 open roles on FindRole.

Listed pay typically runs $163,000–$253,000 across 37 roles with salary data.

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At a glance

TL;DR · Principal Engineer, ASIC Design Verification

Role Posting Log in to save

The Principal Engineer, ASIC Design Verification joins the SOC team within the DRAM Development Lab to develop silicon solutions like AI accelerators and Custom HBM base dies. This role involves participating in verification strategy and methodology definitions, contributing to micro architecture specifications, and verifying modules or subsystems of AI accelerators. You will architect test benches, create test plans, and implement components in UVM to execute verification to closure. Key responsibilities include working with architects to define requirements, closing functional and code coverage targets, and providing post silicon bring up and debug support. Required skills include experience in UVM, C++, and SystemVerilog, along with knowledge of logic and SoC verification. Domain expertise in UCIe, HBM controllers, Memory DFT, and emerging technologies like CXL and LLM accelerators is required.

Skills

UVM SystemVerilog C++ ASIC Verification SoC Verification HBM DDR UCIe Memory DFT CXL AI Accelerators

What you'll do

Participate in the definition of verification strategies and methodologies.
Contribute to micro-architecture specifications and formal reviews.
Verify modules and subsystems of AI accelerators.
Architect test benches and implement components using UVM.
Create and execute test plans to achieve verification closure.
Define verification requirements and close functional and code coverage targets with engineers.
Provide support for post-silicon bring-up and debugging.

What we're looking for

BE in Computer/Electrical Engineering or Computer Science (MS preferred).
20+ years of working experience in ASIC verification (preferred).
Experience in UVM.
Strong language skills including C++ and SystemVerilog.
Experience in logic and SoC verification from planning to closure.
Good understanding of verification flows and tools.
Experience in UCIe, HBM controller, and Memory DFT.
Experience in DDR, Custom HBM, and emerging technologies like CXL or AI LLM accelerators (preferred).

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