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ASIC Implementation Design-for-Test ATPG Tessent TestMax Tetramax Verilog Gate Level Simulation VCS SDF Scan Insertion JTAG Tcl Python Perl Static Timing Analysis Post-Silicon Validation +12 more Show less

Verilog System Verilog DFT MBIST AMBA AXI APB AHB JTAG UPF Formal Verification Linting CDC Checkers Synthesis Post-Silicon Debug RTL +11 more Show less

DFT ASIC Verilog System Verilog ATPG Jtag Scan BIST TestMax Tetramax Tessent PrimeTime VCS Gate Level Simulation Static Timing Analysis Post-Silicon Validation ATE P1687 RTL Physical Design +15 more Show less

Kubernetes Go AWS EKS Docker GitLab CI/CD Kustomize Prometheus Datadog OpenTelemetry gRPC Protocol Buffers Linux DNS TLS Site Reliability Engineering CI/CD +12 more Show less

Secure SDLC DevSecOps Threat Modeling Security Requirements Engineering Build Environment Security Agentic Workflows Automation Secure Architecture & Design Release Management Requirements Engineering +5 more Show less

JavaScript TypeScript React Redux Backbone.js Python GitLab CI/CD DOM Browser APIs Testing Frameworks Source Control Command-line Tools Telemetry AI Tools +10 more Show less

IEC 61508 ISO 26262 FMEA FMEDA FTA DFA HARA IEC 62368 UL 1400-1 Power over Ethernet HVDC Fault Injection Functional Safety Hardware-Software Interfaces +9 more Show less

IEC 61508 ISO 26262 FMEA FMEDA FTA DFA HARA IEC 62368 UL 1400-1 Power over Ethernet HVDC Fault Injection Reliability Assessment Hardware-Software Interfaces +9 more Show less

ASIC DFT Post-Silicon Validation Verilog VCS Gate Level Simulation ATE Patterns P1687 Static Timing Analysis DFT CAD Hardware Bring-up IP Integration Test Architecture Methodology Infrastructure +10 more Show less

ASIC RTL CDC RDC SDC VCS SVA SystemVerilog Synthesis Gate Netlists +5 more Show less

Go Python Kubernetes Docker CI/CD Splunk Terraform Ansible Puppet CloudFormation AWS Azure Google Cloud Platform REST APIs Microservices JavaScript TypeScript React Linux AppDynamics ThousandEyes +16 more Show less

ASIC DFT MBIST Python TCL Perl Verilog System Verilog Synopsys DesignWare SMS TestMax Mentor Graphics Tessent SRAM DRAM +8 more Show less

Python SAML OpenID Connect OAuth 2.0 SCIM WS-Federation AWS SQL Redis React TypeScript REST APIs OpenAPI Microservices Distributed Systems Event-Driven Architecture Architecture Decision Records +12 more Show less

SoC Firmware Software Development Linux x86 GCC Clang PCIe DDR BIOS GPU FPGA Emulation Simnow Root-cause Analysis Performance Profiling RTL +12 more Show less

PCB Design Cadence EMI EMC HVDC Functional Safety IEC 61508 IEC 62368 UL 1400-1 solid--state overcurrent protection Arc Fault Detection Ground Fault Detection +7 more Show less

DFT ASIC Verilog System Verilog ATPG Jtag Scan BIST TestMax Tetramax Tessent PrimeTime VCS Gate Level Simulation Static Timing Analysis Post-Silicon Validation P1687 EDA Tools +13 more Show less