Apple Inc

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About Apple Inc

Published by FindRole · most recent listing October 30, 2026 · Methodology

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3542 open roles on FindRole.

Listed pay typically runs $166,600–$277,600 across 2744 roles with salary data.

Most-posted roles

How Apple Inc posts

Employer behavior measured from this employer’s own listings, including ones that have since closed.

77.5%

of open roles publish a salary range

Layoffs · WARN filings

Trending down

1,074 workers affected across 15 filings since 2023.

— 792 — 282

2023 2024 2025 2026

Source: U.S. Worker Adjustment and Retraining Notification (WARN) Act filings, via WARN Feed (CC BY 4.0).

Open roles

3,542 total

CPU Processor Performance Verification Engineer

Santa Clara, CA 45 days ago $129,300–$194,700

Actively hiring Confirmed live yesterday Trusted Below market

C/C++ Assembly Verilog System Verilog RTL Design CPU Architecture Microarchitecture Performance Modeling Silicon Validation Performance Profiling Digital Logic Design Compiler Techniques

CPU Microarchitect/RTL Engineer

Austin, TX 45 days ago

Actively hiring Confirmed live yesterday Low trust

RTL Verilog VHDL Microarchitecture Logic Design Python Perl Verdi Simulators Waveform Debugging Instruction Fetch and Decode Branch Prediction Register Renaming Out-of-Order Execution Cache and Memory Subsystems

10+ yrs exp

CPU Silicon Validation Engineer

Santa Clara, CA 45 days ago $150,400–$277,600

Actively hiring Confirmed live 2 days ago Low trust Above market

CPU Architecture C C++ Python Perl Assembly ARM ISA FPGA Silicon Bring-up RTL Logic Design Kernel Virtual Machines Memory Management

3+ yrs exp

CPU Microarchitect/RTL Engineer

Austin, TX 45 days ago

Actively hiring Confirmed live yesterday Low trust

RTL Verilog VHDL Microarchitecture Python Perl Logic Design Simulators Verdi Instruction Fetch and Decode Branch Prediction Out-of-Order Execution Cache and Memory Subsystems Power and Area Tradeoffs

3+ yrs exp

CPU Design Verification Engineer

Austin, TX 45 days ago

Actively hiring Confirmed live 2 days ago Low trust

SystemVerilog C C++ Assembly CPU Architecture Digital Logic Design Microarchitecture Post-silicon Bringup Transactors

10+ yrs exp

CPU Top-Level Design Verification Engineer

Santa Clara, CA 45 days ago $129,300–$194,700

Actively hiring Confirmed live yesterday Trusted Below market

SystemVerilog C C++ Python RTL Computer Architecture Assembly Regression Frameworks Waveform Analysis Verification Methodology

CPU Design Verification Engineer

Austin, TX 45 days ago

Actively hiring Confirmed live 2 days ago Low trust

SystemVerilog C C++ Assembly RTL CPU Architecture Digital Logic Design Microarchitecture Transactors Test Plans

3+ yrs exp

CPU Design Verification Engineer

Austin, TX 45 days ago

Actively hiring Confirmed live yesterday Low trust

SystemVerilog C C++ Assembly RTL CPU Architecture Digital Logic Design Microarchitecture Hardware Verification Test Plans Transactors Checkers

CPU CDC/STA Engineer

Santa Clara, CA 45 days ago $150,400–$277,600

Actively hiring Confirmed live yesterday High trust Competitive pay

Static Timing Analysis (STA) Clock Domain Crossing (CDC) Reset Domain Crossing (RDC) SystemVerilog Assertions (SVA) TCL Perl Verilog Spyglass VC-Static PrimeTime Meridian Design Verification Lint RTL

3+ yrs exp

CPU CDC/RDC/STA Engineer

Santa Clara, CA 45 days ago $184,700–$324,800

Actively hiring Confirmed live yesterday High trust Above market

CDC RDC STA SystemVerilog Assertions Verilog TCL Perl Synopsys Real Intent Spyglass VC-Static PrimeTime Meridian RTL Design Design Verification Lint

10+ yrs exp

CPU CDC/RDC/STA Engineer

Beaverton, OR 45 days ago

Actively hiring Confirmed live 2 days ago High trust

CDC RDC STA SystemVerilog Assertions Verilog TCL Perl Synopsys Real Intent Spyglass VC-Static PrimeTime Meridian RTL Design Design Verification

10+ yrs exp

CPU Top-Level Design Verification Engineer

Santa Clara, CA 45 days ago $150,400–$277,600

Actively hiring Confirmed live yesterday Trusted Above market

SystemVerilog C C++ Python RTL Assembly Computer Architecture Regression Frameworks Waveform Analysis Verification Methodology Coverage Convergence Embedded Programming

3+ yrs exp

CPU CDC/STA Engineer

Santa Clara, CA 45 days ago $129,300–$194,700

Actively hiring Confirmed live yesterday High trust Below market

Static Timing Analysis (STA) Clock Domain Crossing (CDC) Reset Domain Crossing (RDC) SystemVerilog Assertions (SVA) Verilog TCL Perl Spyglass VC-Static PrimeTime Meridian Design Verification (DV) Lint RTL

CPU Design Timing Engineer

Santa Clara, CA 45 days ago $184,700–$324,800

Actively hiring Confirmed live 2 days ago Trusted Above market

Static Timing Analysis PrimeTime Tempus TCL Python Perl SDC RTL Logic Synthesis PnR Parasitic Extraction Logic Equivalence clock-domain crossing Assertion Based Verification CPU Microarchitecture

10+ yrs exp

CPU Design Timing Engineer

Beaverton, OR 45 days ago

Actively hiring Confirmed live yesterday Trusted

Static Timing Analysis PrimeTime Tempus TCL Python Perl SDC RTL Logic Synthesis PnR Parasitic Extraction Logic Equivalence clock-domain crossing Assertion Based Verification Variation Modeling Noise Analysis

10+ yrs exp

CPU Processor Power Management Verification Engineer

Santa Clara, CA 45 days ago $184,700–$324,800

Actively hiring Confirmed live 2 days ago Trusted Above market

System Verilog Verilog UVM Python Perl Assembly Formal Verification UPF FPGA Emulation RTL Digital Logic Power Management Clock Control

10+ yrs exp

CPU Design Timing Engineer

Santa Clara, CA 45 days ago $150,400–$277,600

Actively hiring Confirmed live yesterday Trusted Competitive pay

Static Timing Analysis TCL Python Perl PrimeTime Tempus Logic Synthesis PnR Parasitic Extraction Logic Equivalence RTL CPU Microarchitecture Variation Modeling Noise Analysis Scripting

3+ yrs exp

SoC Physical Design Engineer, PnR

Waltham, MA 45 days ago $134,700–$249,500

Actively hiring Confirmed live yesterday Low trust Competitive pay

PnR RTL2GDS STA Physical Verification EMIR Sign-off Floorplanning Clock & Power Distribution Timing Closure Deep Submicron Technology SOC Design Power Optimization

3+ yrs exp

SoC Physical Design Engineer, PnR

Waltham, MA 45 days ago $116,400–$175,200

Actively hiring Confirmed live yesterday Low trust Below market

PnR Physical Design VLSI Verilog VHDL Python Perl TCL SPICE STA DRC LVS EMIR Redhawk Totem Voltus GDS2 Floor-planning Physical Synthesis

CAD Engineer, Custom EMIR Methodology

Sunnyvale, CA 45 days ago $150,400–$277,600

Actively hiring Confirmed live yesterday Low trust Competitive pay

EM/IR Analysis Python Perl C/C++ Layout Design Simulation Extraction Physical Verification Circuit-design Automation

3+ yrs exp