CPU CDC/STA Engineer

Apple Inc

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Quick summary

Work type: On-site
Location: Santa Clara, CA
Salary: $129,300–$194,700 / yr
Posted: 40 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $204k

This role $162k

$113k $279k

below market most similar roles pay here above market

This role pays less than 79% of similar roles. Most pay $175,771–$233,050 — the blue band above. At the midpoint, this role pays about $162k versus about $204k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3497 open roles on FindRole.

Listed pay typically runs $174,149–$277,600 across 2702 roles with salary data.

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At a glance

TL;DR · CPU CDC/STA Engineer

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The CPU CDC/STA Engineer will join the hardware team to analyze designs and drive fixes while developing, maintaining, and improving Lint, Clock Domain Crossing, Reset Domain Crossing, and Static Timing Analysis constraints and methodologies for CPUs across multiple design sites. The role involves developing and maintaining CDC and RDC sign-offs, recommending SystemVerilog assertions to support constraints, and enhancing key STA checks. The engineer will debug vendor tool problems, collaborate with EDA vendor representatives, and work closely with RTL, Verification, CAD, and Physical Design teams. Required skills include a minimum BS degree and scripting experience with TCL or Perl. Preferred experience includes Static Timing Analysis, Clock-Domain Crossing, Reset Domain Crossing, SystemVerilog Assertions, Design Verification Simulations, Verilog, and tools such as Spyglass, VC-Static, PrimeTime, or Meridian.

Skills

Static Timing Analysis (STA) Clock Domain Crossing (CDC) Reset Domain Crossing (RDC) SystemVerilog Assertions (SVA) Verilog TCL Perl Spyglass VC-Static PrimeTime Meridian Design Verification (DV) Lint RTL

What you'll do

Develop, improve, and maintain CDC and RDC sign-offs for CPU designs.
Create and maintain STA constraints and associated sign-off methodologies for CPUs.
Recommend SystemVerilog assertions to support CDC, RDC, and STA constraints.
Debug vendor tool problems and provide solutions to design teams.
Work with EDA vendor representatives to drive new methodologies and tool improvements.
Analyze CPU designs to identify and drive necessary fixes.

What we're looking for

Minimum BS degree.
Scripting experience with TCL or Perl.
Experience in Static Timing Analysis (STA), Clock-Domain Crossing (CDC), or Reset Domain Crossing (RDC) solutions (preferred).
Experience in SystemVerilog Assertions (SVA) and Design Verification (DV) Simulations (preferred).
Knowledge in Spyglass, VC-Static, PrimeTime, or Meridian (preferred).
Experience in Verilog (preferred).

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