Apple Inc

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About Apple Inc

Published by FindRole · most recent listing · Methodology

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3542 open roles on FindRole.

Listed pay typically runs $166,600–$277,600 across 2744 roles with salary data.

Most-posted roles

How Apple Inc posts

Employer behavior measured from this employer’s own listings, including ones that have since closed.

77.5%
of open roles publish a salary range

Layoffs · WARN filings

Trending down

1,074 workers affected across 15 filings since 2023.

Source: U.S. Worker Adjustment and Retraining Notification (WARN) Act filings, via WARN Feed (CC BY 4.0).

Open roles

3,542 total

CPU Power Management Microarchitect/RTL Engineer

Santa Clara, CA 45 days ago $150,400–$277,600
Actively hiring Confirmed live yesterday Trusted Competitive pay
RTL Verilog VHDL Microarchitecture CPU Power Management DVFS DVFM C C++ Python Perl Formal Methods Simulation Emulation Waveform Debugging Logic Design
3+ yrs exp
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CPU Implementation Methodology Engineer

Austin, TX 45 days ago
Actively hiring Confirmed live yesterday High trust
Synthesis PNR VLSI Python TCL STA SAPR Physical Design Logic Optimization PPA Scripting Algorithms
3+ yrs exp
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CPU Implementation Engineer

Austin, TX 45 days ago
Actively hiring Confirmed live 2 days ago Low trust
RTL-to-GDS Synthesis Place-and-Route Perl TCL Logic Design Microarchitecture Microprocessor Architecture Deep Sub-micron Technologies Device Physics
10+ yrs exp
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GPU Power and Performance Characterization Engineer

Austin, TX 45 days ago
Actively hiring Confirmed live yesterday High trust
Python power-management SoC Architecture Data Analysis Dynamic Voltage Frequency Scaling Power Gating Failure Triage Automation Tools Power Measurement Silicon Characterization
3+ yrs exp
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CPU Gate Level Synthesis Engineer

Santa Clara, CA 45 days ago $184,700–$324,800
Actively hiring Confirmed live yesterday High trust Above market
RTL Synthesis Digital Logic Design Physical Design Tcl Python Perl DFT ATPG MBIST Scan Chain Power Analysis RTL Optimization
10+ yrs exp
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CPU Power Management Microarchitect/RTL Engineer

Waltham, MA 45 days ago $165,800–$292,400
Actively hiring Confirmed live 2 days ago Trusted Competitive pay
RTL Verilog VHDL Microarchitecture C C++ Python Perl DVFS DVFM Formal Methods Simulation Emulation Logic Design Power Management
10+ yrs exp
Save

CPU Power Management Microarchitect/RTL Engineer

Santa Clara, CA 45 days ago $184,700–$324,800
Actively hiring Confirmed live 2 days ago Trusted Above market
RTL Verilog VHDL Microarchitecture DVFS DVFM C C++ Python Perl Formal Methods Simulation Emulation Waveform Debugging Logic Design
10+ yrs exp
Save

CPU Power Management Microarchitect/RTL Engineer

Beaverton, OR 45 days ago
Actively hiring Confirmed live yesterday Low trust
RTL Verilog VHDL Microarchitecture C C++ Python Perl DVFS DVFM Formal Methods Simulation Emulation Waveform Debugging Logic Design Clock Generation Asynchronous Clock Crossing
10+ yrs exp
Save

CPU Gate Level Synthesis Engineer

Santa Clara, CA 45 days ago $150,400–$277,600
Actively hiring Confirmed live 3 days ago High trust Competitive pay
RTL Synthesis Digital Logic Design Physical Design TCL Python Perl DFT ATPG MBIST Scan Chain Power Analysis RTL Optimization
3+ yrs exp
Save

CPU Implementation Silicon Correlation Engineer

Santa Clara, CA 45 days ago $184,700–$324,800
Actively hiring Confirmed live yesterday High trust Above market
STA SPICE TCL Perl Python PNR ATPG Silicon Correlation Pre-silicon Design Post-silicon Debug Data Analysis Chip Tapeout Std Cell Architecture Device Technology Spice Models
10+ yrs exp
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CPU Clock Implementation Engineer

Santa Clara, CA 45 days ago $184,700–$324,800
Actively hiring Confirmed live 2 days ago High trust Above market
Physical Design Perl TCL Spice Formal Verification Physical Verification DFM CMOS Circuit Design STA SoC Design Computer Architecture Layout Design Low Power Design
10+ yrs exp
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SoC Physical Design Engineer, STA/Timing

San Jose, CA 45 days ago $150,400–$277,600
Actively hiring Confirmed live yesterday Low trust Competitive pay
STA Timing Closure Perl TCL Physical Design ECO SPICE SoC Circuit Modeling OCV Crosstalk Netlist to Tapeout
3+ yrs exp
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CPU Power Engineer

Santa Clara, CA 45 days ago $184,700–$324,800
Actively hiring Confirmed live 2 days ago Low trust Above market
CPU Architecture RTL Physical Design Python Perl TCL PrimePower PowerArtist STA SPICE CMOS Circuit Design Logic Design Device Physics Auto Place and Route Power Analysis
10+ yrs exp
Save

CPU Power Engineer

Beaverton, OR 45 days ago
Actively hiring Confirmed live yesterday Low trust
CPU Architecture RTL Physical Design Python Perl TCL PrimePower PowerArtist STA SPICE CMOS Circuit Design Logic Design Device Physics Auto Place and Route Power Analysis
10+ yrs exp
Save

CPU Processor Power Management Verification Engineer

Santa Clara, CA 45 days ago $150,400–$277,600
Actively hiring Confirmed live yesterday Trusted Competitive pay
System Verilog Verilog UVM Python Perl Assembly Formal Verification UPF FPGA Emulation RTL Digital Logic Power Management Clock Control Random Constraint Verification
3+ yrs exp
Save

CPU Processor Power Management Verification Engineer

Santa Clara, CA 45 days ago $129,300–$194,700
Actively hiring Confirmed live 2 days ago Trusted Below market
System Verilog Verilog Python Perl TCL Assembly Formal Verification FPGA Emulation RTL Computer Architecture Digital Logic Power Management Clock Control Testbenches Transactors Assertions
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CPU Design Verification Engineer

Santa Clara, CA 45 days ago $129,300–$194,700
Actively hiring Confirmed live yesterday Low trust Below market
C C++ Verilog Assembly Assertions RTL Digital Logic Design Chip Architecture Microarchitecture Silicon Bring-up
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CPU Microarchitect/RTL Engineer

Austin, TX 45 days ago
Actively hiring Confirmed live yesterday Low trust
RTL Verilog VHDL Microarchitecture Python Perl Verdi Logic Design Simulators Waveform Debugging CPU Architecture Performance Verification
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CPU Processor Performance Verification Engineer

Santa Clara, CA 45 days ago $184,700–$324,800
Actively hiring Confirmed live 2 days ago Trusted Above market
CPU Architecture RTL Design System Verilog Verilog C/C++ Assembly Performance Modeling Silicon Validation Performance Tuning Profiling Digital Logic Design Compiler Techniques
10+ yrs exp
Save

CPU Processor Performance Verification Engineer

Santa Clara, CA 45 days ago $150,400–$277,600
Actively hiring Confirmed live 2 days ago Trusted Competitive pay
CPU Architecture RTL Design System Verilog Verilog C/C++ Assembly Performance Modeling Silicon Validation Performance Tuning Profiling Digital Logic Design Scripting
3+ yrs exp
Save