CPU Design Timing Engineer

What you'll do

• Manage all aspects of timing closure for the CPU project.
• Collaborate with RTL and implementation teams to address and implement timing changes.
• Develop and improve timing flows and analysis scripts in coordination with the CAD team.
• Perform static timing analysis using tools like PrimeTime or Tempus.
• Analyze and resolve timing issues across multiple clock and power domains.
• Conduct noise analysis and implement fixes for design noise.
• Model variations and manage SDC constraints including clock definitions and exceptions.
• Analyze data and create representations/plots to improve engineering efficiency.

What we're looking for

• Minimum BS degree and 10+ years of relevant experience.
• Experience with static timing analysis tools such as PrimeTime or Tempus.
• Experience with timing analysis involving multiple clock/power domains, noise analysis, and fixing design noise.
• Experience with variation modeling.
• Experience with TCL and either Perl or Python.
• Experience with SDC command usage including clock definitions, timing exceptions, and IO constraints.
• Prior experience performing timing analysis in high-speed digital designs such as CPUs (preferred).
• Understanding of physical design tools/methodology, deep sub-micron technologies, and CPU microarchitecture (preferred).