Quick summary
- Work type
- On-site
- Location
- —
- Salary
- $150,400–$277,600 / yr
- Posted
- 15 days ago
- Freshness
- Confirmed live yesterday
Market check
Salary context
Competitive pay
How this pay compares to similar roles
Similar $209k
This role $214k
$135k
most similar roles pay here
$293k
This role pays more than 60% of similar roles. Most pay $168,200–$250,000 — the shaded band above. At the midpoint, this role pays about $214k versus about $209k for comparable roles.
Based on 240 similar postings.
Employer
About Apple Inc
Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software
Apple Inc currently has 3513 open roles on FindRole.
Listed pay typically runs $165,800–$277,600 across 2730 roles with salary data.
Most-posted roles
- Software Engineer 287
- Machine Learning Engineer 126
- Engineering Program Manager 64
- Design Verification Engineer 49
- SoC Physical Design Engineer 43
At a glance
TL;DR · CPU Design Timing Engineer
The CPU Design Timing Engineer is responsible for the timing closure of the project while collaborating with implementation, RTL, and CAD teams. The role involves developing timing flows, creating scripts to improve analysis flows and engineer efficiency, and performing extensive work with micro-architects and implementation engineers to drive timing closure for the CPU. Key responsibilities include static timing analysis, noise analysis, variation modeling, and data parsing or plotting. Required technical skills include proficiency in TCL, Perl, or Python, along with experience in tools like PrimeTime or Tempus. The role requires knowledge of physical design methodology including logic synthesis, PnR, parasitic extraction, and logic equivalence. This position focuses on the specific challenge of achieving timing closure within high-speed digital designs such as CPUs while navigating deep sub-micron technologies and scaling trends.
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CPU Design Timing Engineer
Apple Inc
Santa Clara, CA
15 days ago
$184,700–$324,800
Static Timing Analysis
PrimeTime
Tempus
TCL
Python
Perl
SDC
RTL
Physical Design
Logic Synthesis
PnR
Parasitic Extraction
clock-domain crossing
Assertion Based Verification
10+ yrs exp