Apple Inc

3,542 open roles Visit website
Sign in to favorite

Employer

About Apple Inc

Published by FindRole · most recent listing · Methodology

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3542 open roles on FindRole.

Listed pay typically runs $166,600–$277,600 across 2744 roles with salary data.

Most-posted roles

How Apple Inc posts

Employer behavior measured from this employer’s own listings, including ones that have since closed.

77.5%
of open roles publish a salary range

Layoffs · WARN filings

Trending down

1,074 workers affected across 15 filings since 2023.

Source: U.S. Worker Adjustment and Retraining Notification (WARN) Act filings, via WARN Feed (CC BY 4.0).

Open roles

3,542 total

Graphics Power Analysis & Optimization Engineer

Austin, TX 45 days ago
Actively hiring Confirmed live 2 days ago Trusted
Verilog SystemVerilog Python RTL VLSI Digital Logic Design Clock Gating data-gating Power Optimization SoC Power Triage Scripting
Save

GPU Top Level Physical Design Engineer

Santa Clara, CA 45 days ago $184,700–$324,800
Actively hiring Confirmed live 2 days ago Trusted Above market
ASIC Integration Physical Design Floorplanning Place and Route RTL Clock and Power Distribution Global Signal Planning I/O Planning Cadence Synopsys Timing Verification Physical Design Verification Design for Yield Manufacturability multi Vt strategies
10+ yrs exp
Save

GPU Top Level Physical Design Engineer

Austin, TX 45 days ago
Actively hiring Confirmed live yesterday Low trust
ASIC Integration Physical Design Floorplanning Place and Route Clock and Power Distribution Global Signal Planning I/O Planning Cadence Synopsys Timing Verification Physical Design Verification RTL Design for Yield Manufacturability multi Vt strategies ESD Solutions
10+ yrs exp
Save

GPU Top Level Physical Design Engineer

Santa Clara, CA 45 days ago $150,400–$277,600
Actively hiring Confirmed live yesterday Trusted Competitive pay
ASIC Integration Physical Design Floorplanning Place and Route P&R Flows Timing Verification Physical Design Verification Clock and Power Distribution Global Signal Planning I/O Planning Hard IP Integration Mixed Signal Block Integration Design for Yield Manufacturability Multi Vt Strategies RTL Netlist to Tapeout
3+ yrs exp
Save

GPU Top Level Physical Design Engineer

Austin, TX 45 days ago
Actively hiring Confirmed live 2 days ago Low trust
ASIC Integration Physical Design Floorplanning Place and Route Clock and Power Distribution Global Signal Planning I/O Planning Hard IP Integration Timing Verification Physical Design Verification RTL Design for Yield Multi Vt GPU Architecture
3+ yrs exp
Save

GPU Electrical Analysis Engineer

Santa Clara, CA 45 days ago $150,400–$277,600
Actively hiring Confirmed live 2 days ago Trusted Competitive pay
Power Integrity Electromigration Static IR Dynamic Voltage Drop Redhawk Voltus ASIC Integration Floorplanning SPICE Physical Design Verification RDL Routing Bump Planning Power Distribution ESD Analysis SoC Design
3+ yrs exp
Save

GPU Electrical Analysis Engineer

Austin, TX 45 days ago
Actively hiring Confirmed live yesterday Trusted
Power Integrity Electromigration Static IR Dynamic Voltage Drop Redhawk Voltus ASIC Integration Physical Design SPICE Floorplanning Power Distribution Signal Planning RDL Routing Bump Planning ESD Analysis Timing Verification Tapeout
3+ yrs exp
Save

GPU Physical Design Engineer

Santa Clara, CA 45 days ago $150,400–$277,600
Actively hiring Confirmed live yesterday Trusted Competitive pay
ASIC Implementation Physical Design Place and Route Floorplanning Synthesis DFT Clock and Power Distribution RTL Multi-voltage Power Retention Design for Yield Manufacturability Thermal Management Hierarchical Design Top-down Design
3+ yrs exp
Save

GPU Physical Design Engineer

Austin, TX 45 days ago
Actively hiring Confirmed live yesterday Trusted
Physical Design ASIC Implementation Place and Route Floorplanning Synthesis DFT Clock and Power Distribution RTL Multi-voltage Power Retention Design for Yield Manufacturability Thermal Management Tapeout
3+ yrs exp
Save

Graphics FE Integration Engineer

Santa Clara, CA 45 days ago $184,700–$324,800
Actively hiring Confirmed live yesterday Trusted Above market
Verilog System Verilog Python Perl Ruby RTL DFT UPF CPF CDC RDC STA Synthesis Lint LEC Invio Genus PPA Optimization Logic Design Simulation Debugging
10+ yrs exp
Save

Graphics FE Integration Engineer

Austin, TX 45 days ago
Actively hiring Confirmed live yesterday Trusted
Verilog System Verilog Python Perl Ruby RTL UPF CPF CDC RDC STA Synthesis DFT Lint LEC Invio Genus PPA Optimization SIMD Architecture Power Intent
10+ yrs exp
Save

Graphics FE Integration Engineer

Santa Clara, CA 45 days ago $150,400–$277,600
Actively hiring Confirmed live yesterday Trusted Above market
Verilog System Verilog Python Perl Ruby RTL DFT LEC Lint Genus Invio PPA Optimization SIMD Architecture Logic Design
3+ yrs exp
Save

Graphics FE Integration Engineer

Austin, TX 45 days ago
Actively hiring Confirmed live 2 days ago Trusted
Verilog System Verilog Python Perl Ruby RTL Logic Equivalence Checking Lint Synthesis DFT PPA Optimization Invio Genus SIMD Codeline Management
3+ yrs exp
Save

SoC Physical Design Engineer, PnR

Seattle, WA 45 days ago $175,000–$308,500
Actively hiring Confirmed live yesterday Low trust Above market
PnR Physical Design Floorplanning Timing Closure GDS2 Netlist Power Distribution Electrical Verification Design for Yield Manufacturability Multi-vt SOC Design
10+ yrs exp
Save

SoC Physical Design Engineer, PnR

Beaverton, OR 45 days ago
Actively hiring Confirmed live yesterday Low trust
PnR Physical Design Floorplanning Timing Closure GDS2 Netlist Power Distribution Electrical Verification Design for Yield Manufacturability Multi-vt SOC Design
10+ yrs exp
Save

Graphics (GPU) Design Verification Engineer

Austin, TX 45 days ago
Actively hiring Confirmed live yesterday Low trust
System Verilog UVM OVM Universal Verification Methodology Python Ruby Perl VCS Verdi IES DVE HDL SIMD GPU Architecture Functional Coverage Waveform Viewers
10+ yrs exp
Save

Graphics (GPU) Design Verification Engineer

Austin, TX 45 days ago
Actively hiring Confirmed live 2 days ago Low trust
System Verilog C++ UVM OVM Python Ruby Perl VCS Verdi IES DVE HDL SIMD GPU Architecture Functional Coverage Waveform Viewers
3+ yrs exp
Save

Graphics (GPU) Design Verification Engineer

Austin, TX 45 days ago
Actively hiring Confirmed live yesterday Low trust
UVM OVM C++ Verilog Python Ruby Perl HDL SIMD Computer Architecture VCS Verdi IES DVE Functional Coverage Waveform Viewers
Save

Graphics Design Verification Engineer

Austin, TX 45 days ago
Actively hiring Confirmed live 2 days ago Low trust
System Verilog UVM Verilog C++ C OVM HDL GPU Architecture CPU Architecture Constrained Random Verification Assertion Methodology Perl Shell Scripting TCL Makefiles VCS Verdi Perforce RTL Verification
Save