SoC Physical Design Engineer, PnR

As an SoC Physical Design Engineer, PnR, you will be directly responsible for the physical implementation of design partitions from netlist to tapeout for highly complex SOCs utilizing innovative process technology. Working closely with the logic design team, you will drive physical aspects early in the design cycle and manage the full netlist to GDS2 implementation while meeting specific schedule goals. Your daily responsibilities include performing timing, physical, and electrical verification to achieve signoff closure, as well as optimizing partitions for Power, Performance, and Area. You will resolve flow issues and address challenges involving multi-voltage and clock domains, mixed signal block integration, and Design for Yield and Manufacturability. The role requires expertise in floorplanning, power distribution, and industry standard tools to manage large SOC designs exceeding 20M gates at frequencies over 1GHz.