GPU Top Level Physical Design Engineer

What you'll do

• Implement complete chip design from netlist to tapeout.
• Drive physical design aspects early in the design cycle by understanding RTL.
• Develop physical design methodologies, guidelines, and best known methods for GPU design.
• Serve as the focal point for place and route integration at the top level.
• Manage floorplanning, clock and power distribution, and global signal planning.
• Integrate internal and external IP while specifying physical domain requirements.
• Address design for yield, manufacturability, multi-Vt strategies, and thermal management.
• Perform global timing verification and physical design verification flows.

What we're looking for

• BS degree and 10 years of relevant experience.
• Experience with ASIC integration including floorplanning, clock and power distribution, global signal planning, and I/O planning.
• Experience with floorplanning tools and P&R flows using Cadence or Synopsys.
• Experience with floorplanning tools, P&R flows, global timing verification, and Physical Design Verification Flows.
• Experience with hierarchical design approach, top-down design, budgeting, timing, and physical convergence (preferred).
• Experience integrating internal and external vendor IP and specifying physical domain requirements (preferred).
• Experience with multiple voltage and clock domains, ESD solutions, and mixed signal block integration (preferred).
• Experience with large subsystem designs (>20M gates) at frequencies over 1GHz using new technologies (preferred).