Apple Inc

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About Apple Inc

Published by FindRole · most recent listing · Methodology

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3542 open roles on FindRole.

Listed pay typically runs $166,600–$277,600 across 2744 roles with salary data.

Most-posted roles

How Apple Inc posts

Employer behavior measured from this employer’s own listings, including ones that have since closed.

77.5%
of open roles publish a salary range

Layoffs · WARN filings

Trending down

1,074 workers affected across 15 filings since 2023.

Source: U.S. Worker Adjustment and Retraining Notification (WARN) Act filings, via WARN Feed (CC BY 4.0).

Open roles

3,542 total

CPU ML Microarchitect/RTL Engineer

Santa Clara, CA 45 days ago $184,700–$324,800
Actively hiring Confirmed live yesterday Trusted Above market
RTL Verilog VHDL Microarchitecture C C++ Python Perl Formal Methods Simulation Emulation Logic Design Out-of-Order Execution Instruction Scheduling Waveform Debugging
10+ yrs exp
Save

CPU Microarchitect/RTL Engineer, Execution, Load/Store

Waltham, MA 45 days ago $165,800–$292,400
Actively hiring Confirmed live 2 days ago Trusted Competitive pay
RTL Design Microarchitecture Verilog VHDL C C++ Python Perl Logic Design Formal Methods Simulation Emulation Waveform Debugging Out-of-Order Execution Instruction Scheduling Load/Store Execution
10+ yrs exp
Save

CPU Microarchitect/RTL Engineer, Execution, Load/Store

Santa Clara, CA 45 days ago $184,700–$324,800
Actively hiring Confirmed live 2 days ago Trusted Above market
RTL Design Microarchitecture Verilog VHDL C C++ Python Perl Logic Design Formal Methods Simulation Emulation Waveform Debugging Out-of-Order Execution Instruction Scheduling Load/Store Execution
10+ yrs exp
Save

CPU Microarchitect/RTL Engineer, Execution, Load/Store

Beaverton, OR 45 days ago
Actively hiring Confirmed live yesterday Low trust
RTL Design Microarchitecture Verilog VHDL C C++ Python Perl Formal Methods Simulation Emulation Out-of-Order Execution Instruction Scheduling Load/Store Execution Logic Design Waveform Debugging
10+ yrs exp
Save

CAD Engineer, Custom EMIR Methodology

Sunnyvale, CA 45 days ago $150,400–$277,600
Actively hiring Confirmed live yesterday Low trust Competitive pay
EM/IR Analysis Python Perl C/C++ Layout Design Simulation Extraction Physical Verification Circuit-design Automation
3+ yrs exp
Save

CAD Engineer, Custom EMIR Methodology

San Diego, CA 45 days ago $142,300–$263,300
Actively hiring Confirmed live yesterday Low trust Competitive pay
EM/IR Analysis Python Perl C/C++ Layout Design Simulation Extraction Physical Verification Circuit-design
3+ yrs exp
Save

CAD Engineer, Custom EMIR Methodology

Beaverton, OR 45 days ago
Actively hiring Confirmed live 2 days ago Low trust
EM/IR Analysis Python Perl C/C++ Layout Design Simulation Extraction Physical Verification Circuit Verification Automation
3+ yrs exp
Save

CAD Engineer, Custom EMIR Methodology

Austin, TX 45 days ago
Actively hiring Confirmed live yesterday Low trust
EM/IR Analysis Python Perl C/C++ Layout Design Simulation Extraction Physical Verification Circuit Verification Automation
3+ yrs exp
Save

GPU Top RTL Designer

Austin, TX 45 days ago
Actively hiring Confirmed live yesterday Trusted
Verilog System Verilog RTL SoC GPU Timing Analysis Power Intent UPF CDC RDC Logic Simulation Scripting Floor-planning
3+ yrs exp
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CPU Clock Implementation Engineer

Santa Clara, CA 45 days ago $150,400–$277,600
Actively hiring Confirmed live yesterday High trust Competitive pay
Physical Design CMOS Circuit Design Perl TCL Spice STA Parasitic Extraction Physical Verification SoC Design Layout Design Clock Planning Std Cell Architecture
3+ yrs exp
Save

SoC Physical Design Engineer, STA/Timing

San Jose, CA 45 days ago $129,300–$194,700
Actively hiring Confirmed live yesterday Low trust Below market
STA Timing Closure Physical Design Perl TCL SPICE ECO SoC Circuit Modeling OCV Crosstalk
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SoC Physical Design Engineer, STA/Timing

Austin, TX 45 days ago
Actively hiring Confirmed live 2 days ago Low trust
STA Timing Closure Physical Design ECO Perl TCL SPICE SoC OCV Crosstalk Circuit Modeling Netlist to Tapeout
Save

CPU Logic Equivalence Check (LEC) Engineer

Santa Clara, CA 45 days ago $184,700–$324,800
Actively hiring Confirmed live yesterday High trust Above market
Logic Equivalence Check (LEC) Conformal Formality Python TCL Perl RTL-to-gate formal verification Digital logic design Synthesis VCLP ECO CPU implementation Verification flows Scripting
10+ yrs exp
Save

CPU Microarchitect/RTL Engineer

Santa Clara, CA 45 days ago $129,300–$194,700
Actively hiring Confirmed live yesterday Trusted Below market
RTL Verilog VHDL C C++ Python Perl Microarchitecture Formal Verification Simulation Emulation Out-of-Order Execution Branch Prediction
Save

CPU ML Microarchitect/RTL Engineer

Santa Clara, CA 45 days ago $150,400–$277,600
Actively hiring Confirmed live yesterday Trusted Competitive pay
RTL Verilog VHDL Microarchitecture C C++ Python Perl Logic Design Formal Methods Simulation Emulation Waveform Debugging Out-of-Order Execution Memory Subsystems
3+ yrs exp
Save

CPU Microarchitect/RTL Engineer, Execution, Load/Store

Santa Clara, CA 45 days ago $150,400–$277,600
Actively hiring Confirmed live 2 days ago Trusted Competitive pay
RTL Design Microarchitecture Verilog VHDL C C++ Python Perl Logic Design Formal Methods Simulation Emulation Out-of-Order Execution Instruction Scheduling Load/Store Execution
3+ yrs exp
Save

CPU Microarchitect/RTL Engineer, Fetch, Out of Order

Waltham, MA 45 days ago $165,800–$292,400
Actively hiring Confirmed live yesterday Trusted Competitive pay
RTL Design Verilog VHDL Microarchitecture Out-of-Order Execution C C++ Python Perl Formal Methods Simulation Emulation Waveform Debugging Logic Design Instruction Fetch Branch Prediction
10+ yrs exp
Save

CPU Microarchitect/RTL Engineer, Fetch, Out of Order

Santa Clara, CA 45 days ago $184,700–$324,800
Actively hiring Confirmed live yesterday Trusted Above market
RTL Verilog VHDL Microarchitecture Out-of-Order Execution C C++ Python Perl Formal Methods Simulation Emulation Waveform Debugging Logic Design
10+ yrs exp
Save

CPU Microarchitect/RTL Engineer, Fetch, Out of Order

Beaverton, OR 45 days ago
Actively hiring Confirmed live 2 days ago Low trust
RTL Design Microarchitecture Verilog VHDL C C++ Python Perl Formal Methods Simulation Emulation Logic Design Instruction Fetch Branch Prediction Out-of-Order Execution Register Renaming Waveform Debugging
10+ yrs exp
Save

CPU Microarchitect/RTL Engineer, Fetch, Out of Order

Santa Clara, CA 45 days ago $150,400–$277,600
Actively hiring Confirmed live yesterday Trusted Competitive pay
RTL Verilog VHDL Microarchitecture Out-of-Order Execution C C++ Python Perl Formal Methods Simulation Emulation Logic Design Waveform Debugging
3+ yrs exp
Save