GPU Top Level Physical Design Engineer

What you'll do

• Implement complete chip design from netlist to tapeout.
• Drive physical design aspects early in the design cycle based on RTL.
• Develop physical design methodologies, guidelines, and best known methods.
• Serve as the focal point for place and route integration at the top level.
• Manage floorplanning, clock and power distribution, and global signal planning.
• Integrate internal and external IP while specifying physical domain requirements.
• Address design for yield, manufacturability, multi-Vt strategies, and thermal management.
• Supervise progress and drive execution of back-end design goals.

What we're looking for

• BS degree and 3 years of relevant experience.
• Experience with ASIC integration including floorplanning, clock and power distribution, global signal planning, I/O planning, or hard IP integration.
• Experience with hierarchical design approach, top-down design, budgeting, timing, or physical convergence.
• Experience with Floorplanning tools, P&R flows, global timing verification, and Physical Design Verification Flows.
• Experience integrating internal and external vendor IP and specifying physical domain requirements (preferred).
• Experience with multiple voltage and clock domains, ESD solutions, and mixed signal block integration (preferred).
• Experience with large subsystem designs over 20M gates at frequencies exceeding 1GHz using new technologies (preferred).
• Familiarity with Design for Yield, Manufacturability, multi Vt strategies, thermal management, and GPU architecture (preferred).