SoC Physical Design Engineer, PnR

Apple Inc

Confirmed live yesterday High trust

Quick summary

Work type: On-site
Location: Seattle, WA
Salary: $175,000–$308,500 / yr
Posted: 14 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $203k

This role $242k

$131k most similar roles pay here $327k

This role pays more than 80% of similar roles. Most pay $173,906–$231,187 — the shaded band above. At the midpoint, this role pays about $242k versus about $203k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 2925 open roles on FindRole.

Listed pay typically runs $166,600–$277,600 across 2305 roles with salary data.

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At a glance

TL;DR · SoC Physical Design Engineer, PnR

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As an SoC Physical Design Engineer, PnR, you will be responsible for the physical implementation of design partitions from netlist to tapeout for highly complex SOCs utilizing innovative process technology. Working closely with the logic design team, you will drive physical aspects early in the design cycle and manage the full netlist to GDS2 implementation while meeting specific schedule goals. Your daily responsibilities include performing timing, physical, and electrical verification to achieve signoff closure, as well as optimizing partitions for power, performance, and area. You will resolve flow issues and navigate complexities such as multi-voltage domains, mixed signal block integration, and design for yield. The role requires expertise in floorplanning, clock and power distribution, and industry standard tools to manage large SOC designs exceeding 20 million gates at frequencies over 1GHz.

Skills

PnR Floorplanning Timing Closure Physical Design Power Distribution Multi-Vt Netlist to GDS2

What you'll do

Execute netlist to GDS2 implementation for complex SoC partitions.
Drive physical design aspects early in the design cycle with logic teams.
Perform timing, physical, and electrical verification to achieve signoff closure.
Optimize PnR partitions to achieve best Power, Performance, and Area results.
Resolve and improve design and flow issues related to physical design.
Manage floorplanning, clock distribution, and power distribution for large SoC designs.
Address process-related issues including Design for Yield and Manufacturability.
Handle multi-voltage and clock domain integration for mixed-signal blocks.

What we're looking for

Minimum BS degree and 10+ years of relevant industry experience.
MS in Electrical, Electronics, Computer Engineering, or a related field (preferred).
Experience with partition level P&R implementation including floorplanning, clock/power distribution, timing closure, and verification (preferred).
Experience with physical design construction and analysis flows and methodology (preferred).
Experience with large SOC designs exceeding 20M gates at frequencies over 1GHz (preferred).
Familiarity with process-related issues like Design for Yield, Manufacturability, and multi-vt strategies (preferred).
Experience with industry standard tools and understanding their capabilities and algorithms (preferred).
Experience with typical SOC issues such as multiple voltage/clock domains and mixed signal integration (preferred).