Apple Inc

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About Apple Inc

Published by FindRole · most recent listing · Methodology

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3542 open roles on FindRole.

Listed pay typically runs $166,600–$277,600 across 2744 roles with salary data.

Most-posted roles

How Apple Inc posts

Employer behavior measured from this employer’s own listings, including ones that have since closed.

77.5%
of open roles publish a salary range

Layoffs · WARN filings

Trending down

1,074 workers affected across 15 filings since 2023.

Source: U.S. Worker Adjustment and Retraining Notification (WARN) Act filings, via WARN Feed (CC BY 4.0).

Open roles

3,542 total

CAD Engineer, Timing for Gate-Level Flows & Methodologies

San Jose, CA 45 days ago $150,400–$277,600
Actively hiring Confirmed live 2 days ago High trust Competitive pay
Static Timing Analysis STA SoC Python Tcl SDC Gate-Level Flows Timing Closure Timing Analysis Power Reduction Cross-talk Variation
3+ yrs exp
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Physical Design Methodology CAD Engineer

Santa Clara, CA 45 days ago $184,700–$324,800
Actively hiring Confirmed live yesterday Trusted Above market
Physical Design CAD Flow Tcl Python Perl PNR Static Timing Analysis STA RC Extraction Physical Verification EMIR ML GenAI SoC Design
10+ yrs exp
Save

Physical Design Methodology CAD Engineer

San Jose, CA 45 days ago $184,700–$324,800
Actively hiring Confirmed live yesterday Trusted Above market
Physical Design CAD Flow Tcl Python Perl PNR STA RC Extraction EMIR ML GenAI Physical Verification SoC Design
10+ yrs exp
Save

Physical Design Methodology CAD Engineer

San Diego, CA 45 days ago $175,000–$308,500
Actively hiring Confirmed live 2 days ago Trusted Above market
Physical Design CAD Flow Tcl Python Perl PNR Static Timing Analysis STA RC Extraction Physical Verification EMIR GenAI SoC Design
10+ yrs exp
Save

Physical Design Methodology CAD Engineer

Beaverton, OR 45 days ago
Actively hiring Confirmed live yesterday Low trust
Physical Design CAD Flow Tcl Python Perl PNR Static Timing Analysis STA RC Extraction EMIR ML GenAI Physical Verification SoC Design
10+ yrs exp
Save

Physical Design Methodology CAD Engineer

Austin, TX 45 days ago
Actively hiring Confirmed live yesterday Low trust
Physical Design CAD Tcl Python Perl PNR STA RC Extraction EMIR ML GenAI Signoff Physical Verification SoC Design
10+ yrs exp
Save

Physical Design Methodology CAD Engineer

Santa Clara, CA 45 days ago $150,400–$277,600
Actively hiring Confirmed live yesterday Trusted Competitive pay
Physical Design CAD Tools Tcl Python Perl PNR Static Timing Analysis STA RC Extraction EMIR ML GenAI SoC Design Physical Verification
3+ yrs exp
Save

Physical Design Methodology CAD Engineer

San Jose, CA 45 days ago $150,400–$277,600
Actively hiring Confirmed live yesterday Trusted Competitive pay
Physical Design CAD Tools Tcl Python Perl PNR Static Timing Analysis STA RC Extraction EMIR ML GenAI SoC Design Physical Verification
3+ yrs exp
Save

Physical Design Methodology CAD Engineer

San Diego, CA 45 days ago $142,300–$263,300
Actively hiring Confirmed live 2 days ago Trusted Competitive pay
Physical Design CAD Tools Tcl Python Perl PNR Static Timing Analysis STA RC Extraction EMIR ML GenAI SoC Design Physical Verification
3+ yrs exp
Save

Physical Design Methodology CAD Engineer

Austin, TX 45 days ago
Actively hiring Confirmed live 2 days ago Low trust
Physical Design CAD Tools Tcl Python Perl PNR Static Timing Analysis STA RC Extraction EMIR ML GenAI Physical Design Verification Signoff SoC Design
3+ yrs exp
Save

Manager- Technical program management; III-V Photonics

Cupertino, CA 45 days ago $204,400–$306,600
Actively hiring Confirmed live yesterday High trust Above market
III-V Epitaxy Process Integration Process Engineering Product Engineering Quality Engineering DFM Wafer Fab Etch FMEA CpK 8D Reports Optical Semiconductor Technologies LEDs AOI
10+ yrs exp
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SoC Physical Design Engineer, PnR

San Jose, CA 45 days ago $184,700–$324,800
Actively hiring Confirmed live 2 days ago Low trust Above market
PnR Physical Design Floorplanning Timing Closure GDS2 Netlist Power Distribution Electrical Verification Signoff Design for Yield Manufacturability Multi-vt
10+ yrs exp
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SoC Physical Design Engineer, PnR

San Jose, CA 45 days ago $150,400–$277,600
Actively hiring Confirmed live yesterday Low trust Competitive pay
Physical Design PnR Netlist to GDS2 Floorplanning Clock and Power Distribution Timing Closure Electrical Verification SOC Design Signoff Closure
3+ yrs exp
Save

SoC Physical Design Engineer, PnR

San Jose, CA 45 days ago $129,300–$194,700
Actively hiring Confirmed live yesterday Low trust Below market
PnR Physical Design VLSI STA DRC LVS EMIR Redhawk Totem Voltus Verilog VHDL Python Perl TCL SPICE GDS2 Floor-planning Physical Synthesis
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SoC Physical Design Engineer, PnR

Beaverton, OR 45 days ago
Actively hiring Confirmed live 2 days ago Low trust
Physical Design PnR Netlist to GDS2 Floorplanning Clock and Power Distribution Timing Closure Electrical Verification SOC Design Signoff Closure
3+ yrs exp
Save

SoC Physical Design Engineer, PnR

Beaverton, OR 45 days ago
Actively hiring Confirmed live yesterday Low trust
PnR Physical Design Netlist to GDS2 Floorplanning Clock and Power Distribution Timing Closure Electrical Verification Signoff SOC Design Design for Yield Multi-vt
Save

GPU Top RTL Designer

Austin, TX 45 days ago
Actively hiring Confirmed live yesterday Trusted
RTL Verilog System Verilog SoC GPU Timing Analysis CDC RDC UPF Power Management Logic Simulation Floor-planning Scripting Languages
10+ yrs exp
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GPU Top RTL Designer

Austin, TX 45 days ago
Actively hiring Confirmed live 2 days ago High trust
RTL Verilog System Verilog Timing Analysis Logic Simulation Power Management SoC GPU Floor-planning Scripting Power Intent Design Verification
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Graphics Power Analysis & Optimization Engineer

Santa Clara, CA 45 days ago $129,300–$194,700
Actively hiring Confirmed live 2 days ago Trusted Below market
Verilog SystemVerilog Python RTL VLSI Digital Logic Design Clock Gating data-gating SoC Power Optimization Power Estimation Power Sign-off Scripting
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