Graphics Power Analysis & Optimization Engineer

Apple Inc

Confirmed live today High trust

Quick summary

Work type: On-site
Location: —
Salary: $129,300–$194,700 / yr
Posted: 15 days ago
Freshness: Confirmed live today

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $211k

This role $162k

$112k most similar roles pay here $295k

This role pays less than 87% of similar roles. Most pay $181,000–$241,750 — the shaded band above. At the midpoint, this role pays about $162k versus about $211k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3513 open roles on FindRole.

Listed pay typically runs $165,800–$277,600 across 2730 roles with salary data.

Most-posted roles

View all roles at Apple Inc

At a glance

TL;DR · Graphics Power Analysis & Optimization Engineer

Role Posting Log in to save

As a Graphics Power Analysis & Optimization Engineer within the Silicon Technologies group, you will support power activity for high-performance GPU development. You will be responsible for creating early power estimations and targets, performing what-if analyses during architectural evaluation, and supporting RTL and gate-level power rollup. Your daily work involves analyzing various GPU workloads to identify reduction opportunities, implementing optimizations in both RTL and gates, and determining the best sign-off tests to improve analysis coverage. You will also develop flows and heuristics to accelerate triage on large data sets. The role requires proficiency in Verilog, SystemVerilog, and Python scripting. Candidates should possess knowledge of digital logic design principles, VLSI power fundamentals such as dynamic and leakage, and low power techniques like clock gating and data-gating to solve complex power challenges for system-on-chip designs.