CAD Engineer, Timing for Gate-Level Flows & Methodologies

As a member of the STA CAD team within the Silicon Technologies group, the CAD Engineer - Timing for Gate-Level Flows & Methodologies will focus on improving the performance of Apple Silicon. The role involves developing, maintaining, and enhancing gate-level static timing analysis flows while addressing complex timing challenges on advanced technology nodes to ensure first time right silicon. Daily responsibilities include debugging constraints and flow scripts, driving methodology changes for better efficiency, and creating tools for power reduction and timing verification. You will collaborate with design teams and EDA vendors to solve technical problems and incorporate new capabilities. Required skills include experience with static timing analysis tools, programming in Python or Tcl, and an understanding of SDC constraints, noise, cross-talk, variation, and timing margins for large high-performance SoC designs in deep sub-micron technologies.