CAD Engineer, Timing for Gate-Level Flows & Methodologies

What you'll do

• Develop, maintain, and enhance gate-level static timing analysis (STA) flows for silicon designs.
• Debug issues related to constraints, flow scripts, and timing closure with design teams.
• Drive methodology changes to improve efficiency, productivity, and silicon timing correlation.
• Create and maintain scripts and methods for timing analysis and power reduction.
• Develop tools and methodologies to verify timing constraints and establish best practices.
• Analyze timing paths to identify issues and perform post-silicon timing debug.
• Collaborate with EDA vendors to develop new capabilities and solve technical problems.

What we're looking for

• Bachelor of Science degree and 3 years of relevant industry experience.
• Experience with static timing analysis tools and flows (preferred).
• Understanding of programming fundamentals and familiarity with Python, Tcl, or other high-level languages (preferred).
• Familiarity with STA of large high-performance SoC designs in deep sub-micron technologies (preferred).
• Understanding of fundamentals in noise, cross-talk, variation, and timing margins (preferred).
• Knowledge of timing/SDC constraints and hands-on experience in creation/validation (preferred).
• Ability to communicate effectively and describe issues to management while following solutions through to completion.