SoC Physical Design Engineer, PnR

As an SoC Physical Design Engineer, PnR, you will be directly responsible for the physical implementation of design partitions from netlist to tapeout for a highly complex SOC utilizing innovative process technology. Working closely with the logic design team, you will drive physical aspects early in the design cycle and complete netlist to GDS2 implementation while meeting specific schedule and design goals. Your daily responsibilities include timing, physical, and electrical verification, as well as driving signoff closure for partitions. You will identify solutions for flow issues and manage construction and analysis flows. The role requires expertise in floorplanning, clock and power distribution, and experience with large SOC designs exceeding 20M gates at frequencies over 1GHZ using sub 10nm technology nodes while utilizing industry standard tools and algorithms to solve complex physical design challenges.