SoC Physical Design Engineer, PnR

Apple Inc

Confirmed live yesterday High trust

Quick summary

Work type: On-site
Location: Beaverton, OR
Posted: 16 days ago
Freshness: Confirmed live yesterday
Nearby: 99+ roles within 25 mi

Market check

Salary context

How this pay compares to similar roles

Similar $210k

$140k most similar roles pay here $278k

This listing doesn't post a salary. Most similar roles pay $177,250–$241,750.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3553 open roles on FindRole.

Listed pay typically runs $165,800–$277,600 across 2740 roles with salary data.

Most-posted roles

View all roles at Apple Inc

At a glance

TL;DR · SoC Physical Design Engineer, PnR

Role Posting Log in to save

As an SoC Physical Design Engineer, PnR, you will be directly responsible for the physical implementation of design partitions from netlist to tapeout for highly complex SOCs utilizing innovative process technology. Working closely with the logic design team, you will drive physical aspects early in the cycle and manage the full transition to GDS2 while meeting specific schedule goals. Your daily responsibilities include performing timing, physical, and electrical verification to achieve signoff closure, as well as optimizing partitions for Power, Performance, and Area. You will resolve flow issues and navigate complexities such as multi-voltage domains, mixed signal integration, and Design for Yield. The role requires expertise in floorplanning, clock and power distribution, and standard industry tools to manage large SOC designs exceeding 20M gates with frequencies over 1GHz.

Skills

PnR Floorplanning Timing Closure Power Distribution Electrical Verification Netlist to GDS2 Multi-Vt Design for Yield SOC Design

What you'll do

Execute netlist to GDS2 implementation for complex SoC partitions.
Drive physical design aspects early in the design cycle with logic teams.
Perform timing, physical, and electrical verification to achieve signoff closure.
Optimize PnR partitions to achieve best Power, Performance, and Area (PPA).
Resolve and improve design and flow issues related to physical design.
Manage floorplanning, clock distribution, and power distribution for large SoC designs.
Address process-related issues including Design for Yield, Manufacturability, and multi-vt strategies.

What we're looking for

Minimum BS degree and 0+ years of industry experience.
MS in Electrical, Electronics, Computer Engineering, or a related field (preferred).
Experience with partition level P&R implementation including floorplanning, clock/power distribution, timing closure, and verification (preferred).
Experience with physical design construction and analysis flows and methodology (preferred).
Experience with large SOC designs over 20M gates with frequencies exceeding 1GHz (preferred).
Familiarity with process-related issues like Design for Yield, Manufacturability, and multi-vt strategies (preferred).
Experience with industry standard tools and understanding their capabilities and algorithms (preferred).
Experience with typical SOC issues such as multiple voltage/clock domains and mixed signal integration (preferred).

Save