Apple Inc

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About Apple Inc

Published by FindRole · most recent listing · Methodology

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3546 open roles on FindRole.

Listed pay typically runs $166,600–$277,600 across 2746 roles with salary data.

Most-posted roles

How Apple Inc posts

Employer behavior measured from this employer’s own listings, including ones that have since closed.

77.4%
of open roles publish a salary range

Layoffs · WARN filings

Trending down

1,074 workers affected across 15 filings since 2023.

Source: U.S. Worker Adjustment and Retraining Notification (WARN) Act filings, via WARN Feed (CC BY 4.0).

Open roles

3,546 total

Mixed-Signal Behavioral Modeling Engineer

Cupertino, CA 44 days ago $184,700–$324,800
Actively hiring Confirmed live today Trusted Above market
SystemVerilog Python MATLAB SPICE PERL Digital Signal Processing Numerical Analysis Formal Equivalence Co-simulation Behavioral Modeling SERDES Data-converters Circuit Schematics
10+ yrs exp
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Mixed-Signal Behavioral Modeling Engineer

San Diego, CA 44 days ago $175,000–$308,500
Actively hiring Confirmed live yesterday Trusted Above market
SystemVerilog Python MATLAB SPICE PERL Digital Signal Processing Numerical Analysis Formal Equivalence Co-simulation Behavioral Modeling SERDES Data-converters
10+ yrs exp
Save

CPU Power Management Microarchitect/RTL Engineer

Waltham, MA 44 days ago $165,800–$292,400
Actively hiring Confirmed live today Trusted Competitive pay
RTL Verilog VHDL Microarchitecture C C++ Python Perl DVFS DVFM Formal Methods Simulation Emulation Waveform Debugging Logic Design Clock Generation Asynchronous Clock Crossing
10+ yrs exp
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CPU Power Management Microarchitect/RTL Engineer

Santa Clara, CA 44 days ago $184,700–$324,800
Actively hiring Confirmed live yesterday Trusted Above market
RTL Design Microarchitecture Verilog VHDL C C++ Python Perl DVFS DVFM Formal Methods Simulation Emulation Waveform Debugging Logic Design Power Management Clock Generation Asynchronous Clock Crossing
10+ yrs exp
Save

CPU Power Management Microarchitect/RTL Engineer

Beaverton, OR 44 days ago
Actively hiring Confirmed live today Low trust
RTL Verilog VHDL Microarchitecture C C++ Python Perl DVFS DVFM Formal Methods Simulation Emulation Waveform Debugging Logic Design Clock Generation Asynchronous Clock Crossing Power Integrity
10+ yrs exp
Save

CPU Cache Microarchitect/RTL Engineer

Waltham, MA 44 days ago $165,800–$292,400
Actively hiring Confirmed live today Trusted Above market
RTL Verilog VHDL Microarchitecture CPU Cache C C++ Python Perl Formal Methods Simulation Emulation DFT SRAM Coherence Protocols Interconnects
10+ yrs exp
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CPU Cache Microarchitect/RTL Engineer

Santa Clara, CA 44 days ago $184,700–$324,800
Actively hiring Confirmed live today Trusted Above market
RTL Design Verilog VHDL Microarchitecture C C++ Python Perl Formal Methods Simulation Emulation DFT SRAM Design Coherence Protocols Interconnects Power Management
10+ yrs exp
Save

CPU Cache Microarchitect/RTL Engineer

Beaverton, OR 44 days ago
Actively hiring Confirmed live today Low trust
RTL Verilog VHDL Microarchitecture C C++ Python Perl Formal Methods Simulation Emulation DFT SRAM Coherence Protocols Interconnects Power Management
10+ yrs exp
Save

CPU Microarchitect/RTL Engineer, Fetch, Out of Order

Waltham, MA 44 days ago $165,800–$292,400
Actively hiring Confirmed live today Trusted Competitive pay
RTL Design Microarchitecture Verilog VHDL C C++ Python Perl Formal Methods Simulation Emulation Logic Design Out-of-Order Execution Branch Prediction Instruction Fetch Waveform Debugging
10+ yrs exp
Save

CPU Microarchitect/RTL Engineer, Fetch, Out of Order

Santa Clara, CA 44 days ago $184,700–$324,800
Actively hiring Confirmed live today Trusted Above market
RTL Verilog VHDL Microarchitecture Out-of-Order Execution C C++ Python Perl Formal Methods Simulation Emulation Waveform Debugging Logic Design
10+ yrs exp
Save

CPU Microarchitect/RTL Engineer, Fetch, Out of Order

Beaverton, OR 44 days ago
Actively hiring Confirmed live today Low trust
RTL Design Microarchitecture Verilog VHDL C C++ Python Perl Out-of-Order Execution Branch Prediction Instruction Fetch Register Renaming Formal Methods Simulation Emulation Waveform Debugging Logic Design
10+ yrs exp
Save

CPU Performance Engineer

Austin, TX 44 days ago
Actively hiring Confirmed live today Low trust
CPU Performance Architecture Micro-architecture Design C++ C Python Perl Performance Modeling RTL CPU Performance Simulator Performance Analysis OS Internals Compiler Technology Performance Benchmarks
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CPU Performance Engineer

Beaverton, OR 44 days ago
Actively hiring Confirmed live yesterday Low trust
CPU Performance Architecture Micro-architecture Design C++ C Python Perl Performance Modeling RTL Performance Analysis Compiler Technology OS Internals
10+ yrs exp
Save

CPU Performance Engineer

Austin, TX 44 days ago
Actively hiring Confirmed live today Low trust
CPU Performance Architecture Micro-architecture Design C++ C Python Perl Performance Modeling RTL Performance Analysis OS Internals Compiler Technology
10+ yrs exp
Save

CPU Performance Engineer

Austin, TX 44 days ago
Actively hiring Confirmed live yesterday Low trust
CPU Performance Architecture Micro-architecture Design C++ C Python Perl Performance Modeling RTL CPU Performance Simulator OS Internals Compiler Technology Performance Analysis
3+ yrs exp
Save

CPU Power Management Microarchitect/RTL Engineer

Santa Clara, CA 44 days ago $150,400–$277,600
Actively hiring Confirmed live yesterday Trusted Competitive pay
RTL Design Microarchitecture Verilog VHDL C C++ Python Perl DVFS DVFM Formal Methods Simulation Emulation Waveform Debugging Logic Design Power Management
3+ yrs exp
Save

CPU Cache Microarchitect/RTL Engineer

Santa Clara, CA 44 days ago $150,400–$277,600
Actively hiring Confirmed live yesterday Trusted Competitive pay
RTL Design Verilog VHDL Microarchitecture C C++ Python Perl Formal Methods Simulation Emulation DFT SRAM Design Coherence Protocols Interconnects Power Management
3+ yrs exp
Save

RFIC Design Engineer

Sunnyvale, CA 44 days ago $184,700–$324,800
Actively hiring Confirmed live today Trusted Above market
RFIC Analog Design Mixed-Signal RF Circuit Design Cadence Virtuoso Spectre RF Matlab EM Simulation HFSS EMX RFCMOS PLL VCO DCO LOGen Mixers Baseband Filters Silicon Characterization
10+ yrs exp
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RFIC Design Engineer

San Diego, CA 44 days ago $175,000–$308,500
Actively hiring Confirmed live yesterday Trusted Above market
RFIC Analog Design Mixed-Signal RF Circuit Design Cadence Virtuoso Spectre RF Matlab EM Simulation HFSS EMX RFCMOS PLL VCO DCO LOGen Mixers Baseband Filters Silicon Characterization
10+ yrs exp
Save

RFIC Design Engineer

Irvine, CA 44 days ago $175,000–$308,500
Actively hiring Confirmed live today Trusted Above market
RFIC Analog Design Mixed-Signal Cadence Virtuoso Spectre RF Matlab HFSS EMX RFCMOS PLL VCO DCO Mixer Baseband Filters Silicon Characterization Tape-out
10+ yrs exp
Save