CPU Microarchitect/RTL Engineer, Fetch, Out of Order

The CPU Microarchitect/RTL Engineer - Fetch, Out of Order joins the Silicon Engineering Group to drive architecture and RTL development for performant cores. This role involves micro-architecture development and specification from high-level exploration through detailed research, alongside ownership of RTL design to meet specific power, performance, area, and timing goals. The engineer will participate in performance exploration, verification support using formal methods and simulation, and physical design implementation. Key technical requirements include expertise in microprocessor architecture, logic design principles, Verilog or VHDL, and experience with simulators and waveform debugging. Preferred skills include instruction fetch and decode, branch prediction, instruction scheduling, register renaming, out-of-order execution, and low power techniques. Candidates may also utilize C, C++, Perl, or Python to solve complex problems within the CPU front-end and out-of-order subsystems.