CPU Microarchitect/RTL Engineer, Fetch, Out of Order

Apple Inc

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
—
Salary
$165,800–$292,400 / yr
Posted
15 days ago
Freshness
Confirmed live yesterday

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $214k
This role $229k
$133k most similar roles pay here $309k

This role pays more than 66% of similar roles. Most pay $177,300–$250,000 — the shaded band above. At the midpoint, this role pays about $229k versus about $214k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 2925 open roles on FindRole.

Listed pay typically runs $166,600–$277,600 across 2305 roles with salary data.

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At a glance

TL;DR · CPU Microarchitect/RTL Engineer, Fetch, Out of Order

The CPU Microarchitect/RTL Engineer joins the Silicon Engineering Group to drive architecture and RTL development of the CPU front-end and out-of-order subsystem for performant cores. This role involves micro-architecture development from high-level exploration through detailed specification, alongside RTL ownership focused on power, performance, area, and timing goals. The engineer will participate in verification support via test bench development and formal methods, conduct performance exploration to ensure designs meet targets, and collaborate with multi-functional teams for physical design implementation. Required skills include microprocessor architecture knowledge, logic design principles, Verilog or VHDL, and experience with simulators and waveform debugging. Preferred expertise includes instruction fetch, decode, branch prediction, scheduling, register renaming, out-of-order execution, low power techniques, C, C++, Perl, or Python to solve complex high-performance microarchitecture challenges within the processor domain.

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